jspc29.x-matter.uni-frankfurt.de Git - trb5sc.git/blob

   1 //**************************************************************************\r
   2 // *************************************************************************\r
   3 // *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
   4 // *                         PROPRIETARY NOTE                              *\r
   5 // *                                                                       *\r
   6 // *  This software contains information confidential and proprietary      *\r
   7 // *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
   8 // *  in whole or in part, or transferred to other documents, or disclosed *\r
   9 // *  to third parties, or used for any purpose other than that for which  *\r
  10 // *  it was obtained, without the prior written consent of Lattice        *\r
  11 // *  Semiconductor Corporation.  All rights reserved.                     *\r
  12 // *                                                                       *\r
  13 // *************************************************************************\r
  14 //**************************************************************************\r
  15 \r
  16 `timescale 1ns/100ps\r
  17 \r
  18 module register_interface_hb (\r
  19 \r
  20         // Control Signals\r
  21         rst_n,\r
  22         hclk,\r
  23         gbe_mode,\r
  24         sgmii_mode,\r
  25 \r
  26         // Host Bus\r
  27         hcs_n,\r
  28         hwrite_n,\r
  29         haddr,\r
  30         hdatain,\r
  31 \r
  32         hdataout,\r
  33         hready_n,\r
  34 \r
  35         // Register Inputs\r
  36         mr_stat_1000base_x_fd,\r
  37         mr_stat_1000base_x_hd,\r
  38         mr_stat_1000base_t_fd,\r
  39         mr_stat_1000base_t_hd,\r
  40 \r
  41         mr_stat_100base_t4,\r
  42         mr_stat_100base_x_fd,\r
  43         mr_stat_100base_x_hd,\r
  44         mr_stat_10mbps_fd,\r
  45         mr_stat_10mbps_hd,\r
  46         mr_stat_100base_t2_fd,\r
  47         mr_stat_100base_t2_hd,\r
  48 \r
  49         mr_stat_extended_stat,\r
  50         mr_stat_unidir_able,\r
  51         mr_stat_preamb_supr,\r
  52         mr_stat_an_complete,\r
  53         mr_stat_remote_fault,\r
  54         mr_stat_an_able,\r
  55         mr_stat_link_stat,\r
  56         mr_stat_jab_det,\r
  57         mr_stat_extended_cap,\r
  58 \r
  59         mr_page_rx,\r
  60         mr_lp_adv_ability,\r
  61 \r
  62         // Register Outputs\r
  63         mr_main_reset,\r
  64         mr_loopback_enable,\r
  65         mr_speed_selection,\r
  66         mr_an_enable,\r
  67         mr_power_down,\r
  68         mr_isolate,\r
  69         mr_restart_an,\r
  70         mr_duplex_mode,\r
  71         mr_col_test,\r
  72         mr_unidir_enable,\r
  73         mr_adv_ability\r
  74         );\r
  75 \r
  76 \r
  77 input           rst_n ;\r
  78 input           hclk ;\r
  79 input           gbe_mode ;\r
  80 input           sgmii_mode ;\r
  81 \r
  82 input           hcs_n;\r
  83 input           hwrite_n;\r
  84 input    [5:0]  haddr;\r
  85 input    [7:0]  hdatain;\r
  86 \r
  87 output   [7:0]  hdataout;\r
  88 output          hready_n;\r
  89 \r
  90 input           mr_stat_1000base_x_fd;\r
  91 input           mr_stat_1000base_x_hd;\r
  92 input           mr_stat_1000base_t_fd;\r
  93 input           mr_stat_1000base_t_hd;\r
  94 \r
  95 input           mr_stat_100base_t4;\r
  96 input           mr_stat_100base_x_fd;\r
  97 input           mr_stat_100base_x_hd;\r
  98 input           mr_stat_10mbps_fd;\r
  99 input           mr_stat_10mbps_hd;\r
 100 input           mr_stat_100base_t2_fd;\r
 101 input           mr_stat_100base_t2_hd;\r
 102 \r
 103 input           mr_stat_extended_stat;\r
 104 input           mr_stat_unidir_able;\r
 105 input           mr_stat_preamb_supr;\r
 106 input           mr_stat_an_complete;\r
 107 input           mr_stat_remote_fault;\r
 108 input           mr_stat_an_able;\r
 109 input           mr_stat_link_stat;\r
 110 input           mr_stat_jab_det;\r
 111 input           mr_stat_extended_cap;\r
 112 \r
 113 input           mr_page_rx;\r
 114 input [15:0]    mr_lp_adv_ability;\r
 115 \r
 116 output          mr_main_reset;\r
 117 output          mr_loopback_enable;\r
 118 output [1:0]    mr_speed_selection;\r
 119 output          mr_an_enable;\r
 120 output          mr_power_down;\r
 121 output          mr_isolate;\r
 122 output          mr_restart_an;\r
 123 output          mr_duplex_mode;\r
 124 output          mr_col_test;\r
 125 output          mr_unidir_enable;\r
 126 output [15:0]   mr_adv_ability;\r
 127 \r
 128 regs_hb   regs (\r
 129         .rst_n (rst_n),\r
 130         .hclk (hclk),\r
 131 \r
 132         .gbe_mode (gbe_mode),\r
 133         .sgmii_mode (sgmii_mode),\r
 134 \r
 135         .hcs_n (hcs_n),\r
 136         .hwrite_n (hwrite_n),\r
 137         .haddr (haddr),\r
 138         .hdatain (hdatain),\r
 139 \r
 140         .hdataout (hdataout),\r
 141         .hready_n (hready_n),\r
 142 \r
 143         .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd),\r
 144         .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd),\r
 145         .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd),\r
 146         .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd),\r
 147 \r
 148         .mr_stat_100base_t4 (mr_stat_100base_t4),\r
 149         .mr_stat_100base_x_fd (mr_stat_100base_x_fd),\r
 150         .mr_stat_100base_x_hd (mr_stat_100base_x_hd),\r
 151         .mr_stat_10mbps_fd (mr_stat_10mbps_fd),\r
 152         .mr_stat_10mbps_hd (mr_stat_10mbps_hd),\r
 153         .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd),\r
 154         .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd),\r
 155 \r
 156         .mr_stat_extended_stat (mr_stat_extended_stat),\r
 157         .mr_stat_unidir_able (mr_stat_unidir_able),\r
 158         .mr_stat_preamb_supr (mr_stat_preamb_supr),\r
 159         .mr_stat_an_complete (mr_stat_an_complete),\r
 160         .mr_stat_remote_fault (mr_stat_remote_fault),\r
 161         .mr_stat_an_able (mr_stat_an_able),\r
 162         .mr_stat_link_stat (mr_stat_link_stat),\r
 163         .mr_stat_jab_det (mr_stat_jab_det),\r
 164         .mr_stat_extended_cap (mr_stat_extended_cap),\r
 165 \r
 166         .mr_page_rx (mr_page_rx),\r
 167         .mr_lp_adv_ability (mr_lp_adv_ability),\r
 168 \r
 169         .mr_main_reset (mr_main_reset),\r
 170         .mr_loopback_enable (mr_loopback_enable),\r
 171         .mr_speed_selection (mr_speed_selection),\r
 172         .mr_an_enable (mr_an_enable),\r
 173         .mr_power_down (mr_power_down),\r
 174         .mr_isolate (mr_isolate),\r
 175         .mr_restart_an (mr_restart_an),\r
 176         .mr_duplex_mode (mr_duplex_mode),\r
 177         .mr_col_test (mr_col_test),\r
 178         .mr_unidir_enable (mr_unidir_enable),\r
 179 \r
 180         .mr_adv_ability (mr_adv_ability)\r
 181 );\r
 182 endmodule\r
 183 \r
 184 \r
 185 \r
 186 \r
 187 \r
 188 \r
 189 module register_0_hb (\r
 190         rst_n,\r
 191         clk, \r
 192         gbe_mode, \r
 193         cs_0,\r
 194         cs_1,\r
 195         write,\r
 196         ready,\r
 197         data_in,\r
 198 \r
 199         data_out,\r
 200         mr_main_reset,\r
 201         mr_loopback_enable,\r
 202         mr_speed_selection,\r
 203         mr_an_enable,\r
 204         mr_power_down,\r
 205         mr_isolate,\r
 206         mr_restart_an,\r
 207         mr_duplex_mode,\r
 208         mr_col_test,\r
 209         mr_unidir_enable\r
 210 );\r
 211 \r
 212 input           rst_n;\r
 213 input           clk;\r
 214 input           gbe_mode;\r
 215 input           cs_0;\r
 216 input           cs_1;\r
 217 input           write;\r
 218 input           ready;\r
 219 input  [15:0]   data_in;\r
 220 \r
 221 output [15:0]   data_out;\r
 222 output          mr_main_reset; // bit D15 // R/W // Self Clearing\r
 223 output          mr_loopback_enable;     // bit D14 // R/W\r
 224 output [1:0]    mr_speed_selection;     // bit D13 LSB     bit D6 MSB  // R/W\r
 225 output          mr_an_enable;  // bit D12 // R/W\r
 226 output          mr_power_down;          // bit D11 // R/W\r
 227 output          mr_isolate;             // bit D10 // R/W\r
 228 output          mr_restart_an; // bit D09 // R/W // Self Clearing\r
 229 output          mr_duplex_mode;         // bit D08 // STUCK HIGH\r
 230 output          mr_col_test;            // bit D08 // STUCK LOW\r
 231 output          mr_unidir_enable;       // bit D05 // STUCK LOW\r
 232 \r
 233 reg [15:0]      data_out;\r
 234 reg             mr_main_reset;\r
 235 reg             mr_loopback_enable;\r
 236 reg [1:0]       mr_speed_selection;\r
 237 reg             mr_an_enable;\r
 238 reg             mr_power_down = 1'b0;\r
 239 reg             mr_isolate;\r
 240 reg             mr_restart_an;\r
 241 reg             mr_duplex_mode;\r
 242 reg             mr_col_test;\r
 243 reg             mr_unidir_enable;\r
 244 reg             m_m_r;\r
 245 reg             m_r_a;\r
 246 reg             gbe_mode_d1;\r
 247 reg             gbe_mode_d2;\r
 248 \r
 249 \r
 250 \r
 251 // Deboggle\r
 252 always @(posedge clk or negedge rst_n) begin\r
 253         if (rst_n == 1'b0) begin\r
 254                 gbe_mode_d1 <= 0;\r
 255                 gbe_mode_d2 <= 0;\r
 256         end\r
 257         else begin\r
 258                 gbe_mode_d1 <= gbe_mode;\r
 259                 gbe_mode_d2 <= gbe_mode_d1;\r
 260         end\r
 261 end\r
 262 \r
 263 \r
 264 \r
 265 // Write Operations\r
 266 \r
 267         // Low Portion of Register[D7:D0] has no\r
 268         // implemented bits.  Therefore, no write\r
 269         // operations here.\r
 270 \r
 271         // High Portion of Register[D15:D8]\r
 272         always @(posedge clk or negedge rst_n) begin\r
 273                 if (rst_n == 1'b0) begin\r
 274                         mr_main_reset <= 1'b0;\r
 275                         mr_loopback_enable <= 1'b0;\r
 276                         mr_speed_selection <= 2'b10;\r
 277                         mr_an_enable <= 1'b1;\r
 278                         mr_power_down <= 1'b0;\r
 279                         mr_isolate <= 1'b0;\r
 280                         mr_restart_an <= 1'b0;\r
 281                         mr_duplex_mode <= 1'b1;\r
 282                         mr_col_test <= 1'b0;\r
 283                         mr_unidir_enable <= 1'b0;\r
 284                         m_m_r <= 0;\r
 285                         m_r_a <= 0;\r
 286                 end\r
 287                 else begin\r
 288 \r
 289                         // defaults\r
 290                         mr_duplex_mode <= 1'b1;   // STUCK HIGH\r
 291                         mr_col_test <= 1'b0;      // STUCK LOW\r
 292 \r
 293                         // Do the Writes\r
 294                         if (cs_1 && ready && write) begin\r
 295                                 mr_main_reset <= data_in[15];\r
 296                                 mr_loopback_enable      <= data_in[14];\r
 297                                 mr_an_enable <= data_in[12];\r
 298                                 mr_power_down           <= data_in[11];\r
 299                                 mr_isolate              <= data_in[10];\r
 300                                 mr_restart_an <= data_in[9];\r
 301                         end\r
 302 \r
 303 \r
 304                         // Manage Writes to Speed Selection Based on GBE MODE\r
 305                         if (gbe_mode_d2) begin\r
 306                                 mr_speed_selection[1:0] <= 2'b10; // STUCK AT 1GBPS\r
 307                         end\r
 308                         else begin\r
 309                                 if (cs_1 && ready && write) begin\r
 310                                         mr_speed_selection[0]   <= data_in[13];\r
 311                                 end\r
 312                                 if (cs_0 && ready && write) begin\r
 313                                         mr_speed_selection[1]   <= data_in[6];\r
 314                                         mr_unidir_enable        <= data_in[5];\r
 315                                 end\r
 316                         end\r
 317 \r
 318 \r
 319 \r
 320                         // Delay the Self Clearing Register Bits\r
 321                         m_m_r <= mr_main_reset;\r
 322                         m_r_a <= mr_restart_an;\r
 323 \r
 324                         // Do the Self Clearing\r
 325                         if (m_m_r)\r
 326                                 mr_main_reset <= 0;\r
 327 \r
 328                         if (m_r_a)\r
 329                                 mr_restart_an <= 0;\r
 330                 end\r
 331         end\r
 332 \r
 333 \r
 334 \r
 335 \r
 336 \r
 337 // Read Operations\r
 338         always @(*) begin\r
 339                         data_out[7] <= mr_col_test;\r
 340                         data_out[6] <= mr_speed_selection[1];\r
 341                         data_out[5] <= mr_unidir_enable;\r
 342                         data_out[4] <= 1'b0;\r
 343                         data_out[3] <= 1'b0;\r
 344                         data_out[2] <= 1'b0;\r
 345                         data_out[1] <= 1'b0;\r
 346                         data_out[0] <= 1'b0;\r
 347 \r
 348                         data_out[15] <= mr_main_reset;\r
 349                         data_out[14] <= mr_loopback_enable;\r
 350                         data_out[13] <= mr_speed_selection[0];\r
 351                         data_out[12] <= mr_an_enable;\r
 352                         data_out[11] <= mr_power_down;\r
 353                         data_out[10] <= mr_isolate;\r
 354                         data_out[9]  <= mr_restart_an;\r
 355                         data_out[8]  <= mr_duplex_mode;\r
 356         end\r
 357 endmodule\r
 358 \r
 359 module register_1_hb (\r
 360         rst_n,\r
 361         clk,\r
 362         cs_0,\r
 363         cs_1,\r
 364         write,\r
 365         ready,\r
 366 \r
 367 \r
 368         mr_stat_100base_t4,\r
 369         mr_stat_100base_x_fd,\r
 370         mr_stat_100base_x_hd,\r
 371         mr_stat_10mbps_fd,\r
 372         mr_stat_10mbps_hd,\r
 373         mr_stat_100base_t2_fd,\r
 374         mr_stat_100base_t2_hd,\r
 375 \r
 376         mr_stat_extended_stat,\r
 377         mr_stat_unidir_able,\r
 378         mr_stat_preamb_supr,\r
 379         mr_stat_an_complete,\r
 380         mr_stat_remote_fault,\r
 381         mr_stat_an_able,\r
 382         mr_stat_link_stat,\r
 383         mr_stat_jab_det,\r
 384         mr_stat_extended_cap,\r
 385 \r
 386         data_out\r
 387 );\r
 388 \r
 389 input           rst_n;\r
 390 input           clk;\r
 391 input           cs_0;\r
 392 input           cs_1;\r
 393 input           write;\r
 394 input           ready;\r
 395 input           mr_stat_100base_t4;     // bit D15 // Read-Only\r
 396 input           mr_stat_100base_x_fd;   // bit D14 // Read-Only\r
 397 input           mr_stat_100base_x_hd;   // bit D13 // Read-Only\r
 398 input           mr_stat_10mbps_fd;      // bit D12 // Read-Only\r
 399 input           mr_stat_10mbps_hd;      // bit D11 // Read-Only\r
 400 input           mr_stat_100base_t2_fd;  // bit D10 // Read-Only\r
 401 input           mr_stat_100base_t2_hd;  // bit D9  // Read-Only\r
 402 \r
 403 input           mr_stat_extended_stat;  // bit D8  // Read-Only\r
 404 input           mr_stat_unidir_able;    // bit D7  // Read-Only\r
 405 input           mr_stat_preamb_supr;    // bit D6  // Read-Only\r
 406 input           mr_stat_an_complete;    // bit D5  // Read-Only\r
 407 input           mr_stat_remote_fault;   // bit D4  // Read-Only\r
 408 input           mr_stat_an_able;        // bit D3  // Read-Only\r
 409 input           mr_stat_link_stat;      // bit D2  // Read-Only // Latch-On-Zero // Clear-On-Read\r
 410 input           mr_stat_jab_det;        // bit D1  // Read-Only\r
 411 input           mr_stat_extended_cap;   // bit D0  // Read-Only\r
 412 \r
 413 output [15:0]   data_out;\r
 414 \r
 415 reg [15:0]      data_out;\r
 416 \r
 417 reg             link_stat_d1;\r
 418 reg             link_stat_d2;\r
 419 reg             clear_on_read;\r
 420 reg             read_detect;\r
 421 reg             rd_d1;\r
 422 reg             rd_d2;\r
 423 reg             allow_link_stat;\r
 424 reg             link_ok_status;\r
 425 // metastability filter\r
 426         always @(posedge clk or negedge rst_n) begin\r
 427                 if (rst_n == 1'b0) begin\r
 428                         link_stat_d1 <= 1'b0;\r
 429                         link_stat_d2 <= 1'b0;\r
 430                 end\r
 431                 else begin\r
 432                         link_stat_d1 <= mr_stat_link_stat;\r
 433                         link_stat_d2 <= link_stat_d1;\r
 434                 end\r
 435         end\r
 436 \r
 437 // generate clear-on-read signal\r
 438         always @(posedge clk or negedge rst_n) begin\r
 439                 if (rst_n == 1'b0) begin\r
 440                         clear_on_read <= 1'b0;\r
 441                         read_detect <= 1'b0;\r
 442                         rd_d1 <= 1'b0;\r
 443                         rd_d2 <= 1'b0;\r
 444                 end\r
 445                 else begin\r
 446                         if (!write && ready && cs_0)\r
 447                                 read_detect <= 1'b1;\r
 448                         else \r
 449                                 read_detect <= 1'b0;\r
 450 \r
 451                         rd_d1 <= read_detect;\r
 452                         rd_d2 <= rd_d1;\r
 453 \r
 454                         // assert on falling edge of rd_d2\r
 455                         clear_on_read <= !rd_d1 & rd_d2;\r
 456                 end\r
 457         end\r
 458 \r
 459 \r
 460 // Latch and Clear\r
 461         always @(posedge clk or negedge rst_n) begin\r
 462                 if (rst_n == 1'b0) begin\r
 463                         allow_link_stat <= 1'b0;\r
 464                         link_ok_status <= 1'b0;\r
 465                 end\r
 466                 else begin\r
 467 \r
 468                         case (allow_link_stat)\r
 469                                 1'b0: begin\r
 470                                         if (clear_on_read) begin\r
 471                                                 allow_link_stat<= 1'b1;\r
 472                                         end\r
 473                                 end\r
 474 \r
 475                                 1'b1: begin\r
 476                                         if (!link_stat_d2) begin\r
 477                                                 allow_link_stat <= 1'b0;\r
 478                                         end\r
 479                                 end\r
 480                         endcase\r
 481 \r
 482 \r
 483                         if (allow_link_stat) begin\r
 484                                 // allow status shoot-thru after clear-on-read\r
 485                                 link_ok_status <= link_stat_d2;\r
 486                         end\r
 487                         else begin\r
 488                                 // force status low when link IS NOT_OKAY\r
 489                                 link_ok_status <= 1'b0;\r
 490                         end\r
 491 \r
 492                 end\r
 493         end\r
 494 \r
 495 \r
 496 // Read Operations\r
 497 \r
 498         always @(*) begin\r
 499                         data_out[7] <= mr_stat_unidir_able;\r
 500                         data_out[6] <= mr_stat_preamb_supr;\r
 501                         data_out[5] <= mr_stat_an_complete;\r
 502                         data_out[4] <= mr_stat_remote_fault;\r
 503                         data_out[3] <= mr_stat_an_able;\r
 504                         data_out[2] <= link_ok_status;\r
 505                         data_out[1] <= mr_stat_jab_det;\r
 506                         data_out[0] <= mr_stat_extended_cap;\r
 507 \r
 508                         data_out[15] <= mr_stat_100base_t4;\r
 509                         data_out[14] <= mr_stat_100base_x_fd;\r
 510                         data_out[13] <= mr_stat_100base_x_hd;\r
 511                         data_out[12] <= mr_stat_10mbps_fd;\r
 512                         data_out[11] <= mr_stat_10mbps_hd;\r
 513                         data_out[10] <= mr_stat_100base_t2_fd;\r
 514                         data_out[9]  <= mr_stat_100base_t2_hd;\r
 515                         data_out[8]  <= mr_stat_extended_stat;\r
 516         end\r
 517 endmodule\r
 518 \r
 519 module register_4_hb (\r
 520         rst_n,\r
 521         clk, \r
 522         gbe_mode,\r
 523         sgmii_mode,\r
 524         cs_0,\r
 525         cs_1,\r
 526         write,\r
 527         ready,\r
 528         data_in,\r
 529 \r
 530         data_out,\r
 531         mr_adv_ability\r
 532 );\r
 533 \r
 534 parameter [15:0] initval_gbe = 16'h0020;\r
 535 parameter [15:0] initval_phy = 16'hd801;\r
 536 parameter [15:0] initval_mac = 16'h4001;\r
 537 \r
 538 input           rst_n;\r
 539 input           clk;\r
 540 input           gbe_mode;\r
 541 input           sgmii_mode;\r
 542 input           cs_0;\r
 543 input           cs_1;\r
 544 input           write;\r
 545 input           ready;\r
 546 input  [15:0]   data_in;\r
 547 \r
 548 output [15:0]   data_out;\r
 549 output [15:0]   mr_adv_ability; // When sgmii_mode == 1 == PHY\r
 550                                 // all bits D15-D0 are R/W,\r
 551                                 ///////////////////////////////////\r
 552                                 // D15 = Link Status (1=up, 0=down)\r
 553                                 // D14 = Can be written but has no effect\r
 554                                 //           on autonegotiation.  Instead\r
 555                                 //           the autonegotiation state machine\r
 556                                 //           controls the utilization of this bit.\r
 557                                 // D12 = Duplex Mode (1=full, 0=half)\r
 558                                 // D11:10 = Speed (11=reserved)\r
 559                                 //                (10=1000Mbps)\r
 560                                 //                (01=100 Mbps)\r
 561                                 //                (00=10  Mbps)\r
 562                                 // D0 = 1\r
 563                                 // all other bits = 0\r
 564                                 ///////////////////////////////////\r
 565                                 //When sgmii_mode == 0 = MAC\r
 566                                 // all bits D15-D0 are R/W,\r
 567                                 // D14 = Can be written but has no effect\r
 568                                 //           on autonegotiation.  Instead\r
 569                                 //           the autonegotiation state machine\r
 570                                 //           controls the utilization of this bit.\r
 571                                 // D0 = 1\r
 572                                 // all other bits = 0\r
 573                                 ///////////////////////////////////\r
 574 \r
 575 \r
 576 reg [15:0]      data_out;\r
 577 reg [15:0]      mr_adv_ability;\r
 578 reg             rst_d1;\r
 579 reg             rst_d2;\r
 580 reg             rst_d3;\r
 581 reg             rst_d4;\r
 582 reg             rst_d5;\r
 583 reg             rst_d6;\r
 584 reg             rst_d7;\r
 585 reg             rst_d8;\r
 586 reg             sync_reset;\r
 587 reg             sgmii_mode_d1;\r
 588 reg             sgmii_mode_d2;\r
 589 reg             sgmii_mode_d3;\r
 590 reg             sgmii_mode_d4;\r
 591 reg             sgmii_mode_change;\r
 592 reg             gbe_mode_d1;\r
 593 reg             gbe_mode_d2;\r
 594 reg             gbe_mode_d3;\r
 595 reg             gbe_mode_d4;\r
 596 reg             gbe_mode_change;\r
 597 \r
 598 // generate a synchronous reset signal\r
 599 //    note: this method is used so that\r
 600 //          an initval can be applied during\r
 601 //          device run-time, instead of at compile time\r
 602 always @(posedge clk or negedge rst_n) begin\r
 603         if (rst_n == 1'b0) begin\r
 604                 rst_d1 <= 0;\r
 605                 rst_d2 <= 0;\r
 606                 rst_d3 <= 0;\r
 607                 rst_d4 <= 0;\r
 608                 rst_d5 <= 0;\r
 609                 rst_d6 <= 0;\r
 610                 rst_d7 <= 0;\r
 611                 rst_d8 <= 0;\r
 612                 sync_reset <= 0;\r
 613         end\r
 614         else begin\r
 615                 rst_d1 <= 1;\r
 616                 rst_d2 <= rst_d1;\r
 617                 rst_d3 <= rst_d2;\r
 618                 rst_d4 <= rst_d3;\r
 619                 rst_d5 <= rst_d4;\r
 620                 rst_d6 <= rst_d5;\r
 621                 rst_d7 <= rst_d6;\r
 622                 rst_d8 <= rst_d7;\r
 623 \r
 624                 // asserts on rising edge of rst_d8\r
 625                 sync_reset <= !rst_d8 & rst_d7; \r
 626         end\r
 627 end\r
 628 \r
 629 \r
 630 // Detect change in sgmii_mode\r
 631 always @(posedge clk or negedge rst_n) begin\r
 632         if (rst_n == 1'b0) begin\r
 633                 sgmii_mode_d1 <= 0;\r
 634                 sgmii_mode_d2 <= 0;\r
 635                 sgmii_mode_d3 <= 0;\r
 636                 sgmii_mode_d4 <= 0;\r
 637                 sgmii_mode_change <= 0;\r
 638         end\r
 639         else begin\r
 640 \r
 641                 // deboggle\r
 642                 sgmii_mode_d1 <= sgmii_mode;\r
 643                 sgmii_mode_d2 <= sgmii_mode_d1;\r
 644 \r
 645                 // delay \r
 646                 sgmii_mode_d3 <= sgmii_mode_d2;\r
 647                 sgmii_mode_d4 <= sgmii_mode_d3;\r
 648 \r
 649                 // detect change\r
 650                 if (sgmii_mode_d3 != sgmii_mode_d4)\r
 651                         sgmii_mode_change <= 1;\r
 652                 else\r
 653                         sgmii_mode_change <= 0;\r
 654         end\r
 655 end\r
 656 \r
 657 \r
 658 // Detect change in gbe_mode\r
 659 always @(posedge clk or negedge rst_n) begin\r
 660         if (rst_n == 1'b0) begin\r
 661                 gbe_mode_d1 <= 0;\r
 662                 gbe_mode_d2 <= 0;\r
 663                 gbe_mode_d3 <= 0;\r
 664                 gbe_mode_d4 <= 0;\r
 665                 gbe_mode_change <= 0;\r
 666         end\r
 667         else begin\r
 668 \r
 669                 // deboggle\r
 670                 gbe_mode_d1 <= gbe_mode;\r
 671                 gbe_mode_d2 <= gbe_mode_d1;\r
 672 \r
 673                 // delay \r
 674                 gbe_mode_d3 <= gbe_mode_d2;\r
 675                 gbe_mode_d4 <= gbe_mode_d3;\r
 676 \r
 677                 // detect change\r
 678                 if (gbe_mode_d3 != gbe_mode_d4)\r
 679                         gbe_mode_change <= 1;\r
 680                 else\r
 681                         gbe_mode_change <= 0;\r
 682         end\r
 683 end\r
 684 \r
 685 \r
 686 // Write Operations\r
 687         // Low Portion of Register[D7:D0]\r
 688         always @(posedge clk or negedge rst_n) begin\r
 689                 if (rst_n == 1'b0) begin\r
 690                         mr_adv_ability[7:0] <= 8'h01;\r
 691                 end\r
 692                 else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
 693                         if (gbe_mode_d4)\r
 694                                 mr_adv_ability[7:0] <= initval_gbe[7:0];\r
 695                         else if (sgmii_mode)\r
 696                                 mr_adv_ability[7:0] <= initval_phy[7:0];\r
 697                         else\r
 698                                 mr_adv_ability[7:0] <= initval_mac[7:0];\r
 699                 end\r
 700                 else begin\r
 701                         if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin\r
 702                                 mr_adv_ability[7:0] <= data_in[7:0];\r
 703                         end\r
 704                 end\r
 705         end\r
 706 \r
 707 \r
 708         // High Portion of Register[D15:D8]\r
 709         always @(posedge clk or negedge rst_n) begin\r
 710                 if (rst_n == 1'b0) begin\r
 711                         mr_adv_ability[15:8] <= 8'h40; // default\r
 712                 end\r
 713                 else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
 714                         if (gbe_mode_d4)\r
 715                                 mr_adv_ability[15:8] <= initval_gbe[15:8];\r
 716                         else if (sgmii_mode)\r
 717                                 mr_adv_ability[15:8] <= initval_phy[15:8];\r
 718                         else\r
 719                                 mr_adv_ability[15:8] <= initval_mac[15:8];\r
 720                 end\r
 721                 else begin\r
 722                         if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin\r
 723                                 mr_adv_ability[15:8] <= data_in[15:8];\r
 724                         end\r
 725                 end\r
 726         end\r
 727 \r
 728 \r
 729 \r
 730 \r
 731 \r
 732 \r
 733 \r
 734 \r
 735 \r
 736 // Read Operations\r
 737 \r
 738         always @(*) begin\r
 739                         data_out[7:0] <= mr_adv_ability[7:0];\r
 740                         data_out[15:8] <= mr_adv_ability[15:8];\r
 741         end\r
 742 \r
 743 endmodule\r
 744 \r
 745 \r
 746 \r
 747 \r
 748 \r
 749 \r
 750 module register_5_hb (\r
 751         rst_n,\r
 752         mr_lp_adv_ability,\r
 753         cs_0,\r
 754         cs_1,\r
 755         ready,\r
 756 \r
 757         data_out\r
 758 );\r
 759 \r
 760 input           rst_n;\r
 761 input           cs_0;\r
 762 input           cs_1;\r
 763 input           ready;\r
 764 input  [15:0]   mr_lp_adv_ability;\r
 765                                 // This entire register is read-only\r
 766                                 ///////////////////////////////////\r
 767                                 // When sgmii_mode == 0 == MAC\r
 768                                 ///////////////////////////////////\r
 769                                 // D15 = PHY Link Status (1=up, 0=down)\r
 770                                 // D14 = PHY Autonegotiation Handshake\r
 771                                 // D12 = PHY Duplex Mode (1=full, 0=half)\r
 772                                 // D11:10 = PHY Speed (11=reserved)\r
 773                                 //                    (10=1000Mbps)\r
 774                                 //                    (01=100 Mbps)\r
 775                                 //                    (00=10  Mbps)\r
 776                                 // D0 = 1\r
 777                                 // all other bits = 0\r
 778                                 ///////////////////////////////////\r
 779                                 //When sgmii_mode == 1 = PHY\r
 780                                 // D14 = MAC Autonegotiation Handshake\r
 781                                 // D0 = 1\r
 782                                 // all other bits = 0\r
 783                                 ///////////////////////////////////\r
 784 output [15:0]   data_out;\r
 785 \r
 786 reg [15:0]      data_out;\r
 787 \r
 788 // Read Operations\r
 789 \r
 790         always @(*) begin\r
 791                         data_out[7:0] <= mr_lp_adv_ability[7:0];\r
 792                         data_out[15:8] <= mr_lp_adv_ability[15:8];\r
 793         end\r
 794 endmodule\r
 795 \r
 796 module register_6_hb (\r
 797         rst_n,\r
 798         clk,\r
 799         mr_page_rx,\r
 800         cs_0,\r
 801         cs_1,\r
 802         write,\r
 803         ready,\r
 804 \r
 805         data_out\r
 806 );\r
 807 \r
 808 input           rst_n;\r
 809 input           clk;\r
 810 input           cs_0;\r
 811 input           cs_1;\r
 812 input           write;\r
 813 input           ready;\r
 814 input           mr_page_rx;\r
 815 output [15:0]   data_out;\r
 816 \r
 817 reg [15:0]      data_out;\r
 818 reg             mr_page_rx_latched;\r
 819 reg             clear_on_read;\r
 820 reg             read_detect;\r
 821 reg             rd_d1;\r
 822 reg             rd_d2;\r
 823 \r
 824 // generate clear-on-read signal\r
 825         always @(posedge clk or negedge rst_n) begin\r
 826                 if (rst_n == 1'b0) begin\r
 827                         clear_on_read <= 0;\r
 828                         read_detect <= 0;\r
 829                         rd_d1 <= 0;\r
 830                         rd_d2 <= 0;\r
 831                 end\r
 832                 else begin\r
 833                         if (!write && ready && cs_0)\r
 834                                 read_detect <= 1;\r
 835                         else \r
 836                                 read_detect <= 0;\r
 837 \r
 838                         rd_d1 <= read_detect;\r
 839                         rd_d2 <= rd_d1;\r
 840 \r
 841                         // assert on falling edge of rd_d2\r
 842                         clear_on_read <= !rd_d1 & rd_d2;\r
 843                 end\r
 844         end\r
 845 \r
 846 \r
 847 // Latch and Clear\r
 848         always @(posedge clk or negedge rst_n) begin\r
 849                 if (rst_n == 1'b0) begin\r
 850                         mr_page_rx_latched <= 0;\r
 851                 end\r
 852                 else begin\r
 853                         if (clear_on_read)\r
 854                                 mr_page_rx_latched <= 0;\r
 855                         else if (mr_page_rx)\r
 856                                 mr_page_rx_latched <= 1;\r
 857                 end\r
 858         end\r
 859 \r
 860 \r
 861 // Read Operations\r
 862 \r
 863         always @(*) begin\r
 864                         data_out[15:2] <= 14'd0;\r
 865                         data_out[1] <= mr_page_rx_latched;\r
 866                         data_out[0] <= 0;\r
 867         end\r
 868 endmodule\r
 869 \r
 870 \r
 871 module register_f_hb (\r
 872         rst_n,\r
 873         cs_0,\r
 874         cs_1,\r
 875 \r
 876         mr_stat_1000base_x_fd,\r
 877         mr_stat_1000base_x_hd,\r
 878         mr_stat_1000base_t_fd,\r
 879         mr_stat_1000base_t_hd,\r
 880 \r
 881         data_out\r
 882 );\r
 883 \r
 884 input           rst_n;\r
 885 input           cs_0;\r
 886 input           cs_1;\r
 887 \r
 888 input           mr_stat_1000base_x_fd;  // bit D15 // Read-Only\r
 889 input           mr_stat_1000base_x_hd;  // bit D14 // Read-Only\r
 890 input           mr_stat_1000base_t_fd;  // bit D13 // Read-Only\r
 891 input           mr_stat_1000base_t_hd;  // bit D12 // Read-Only\r
 892 \r
 893 output [15:0]   data_out;\r
 894 \r
 895 reg [15:0]      data_out;\r
 896 \r
 897 \r
 898 // Read Operations\r
 899 \r
 900         always @(*) begin\r
 901                         data_out[7] <= 1'b0;\r
 902                         data_out[6] <= 1'b0;\r
 903                         data_out[5] <= 1'b0;\r
 904                         data_out[4] <= 1'b0;\r
 905                         data_out[3] <= 1'b0;\r
 906                         data_out[2] <= 1'b0;\r
 907                         data_out[1] <= 1'b0;\r
 908                         data_out[0] <= 1'b0;\r
 909 \r
 910                         data_out[15] <= mr_stat_1000base_x_fd;\r
 911                         data_out[14] <= mr_stat_1000base_x_hd;\r
 912                         data_out[13] <= mr_stat_1000base_t_fd;\r
 913                         data_out[12] <= mr_stat_1000base_t_hd;\r
 914                         data_out[11] <= 1'b0;\r
 915                         data_out[10] <= 1'b0;\r
 916                         data_out[9]  <= 1'b0;\r
 917                         data_out[8]  <= 1'b0;\r
 918         end\r
 919 endmodule\r
 920 \r
 921 \r
 922 module regs_hb (\r
 923         rst_n,\r
 924         hclk,\r
 925         gbe_mode,\r
 926         sgmii_mode,\r
 927         hcs_n,\r
 928         hwrite_n,\r
 929         haddr,\r
 930         hdatain,\r
 931 \r
 932         hdataout,\r
 933         hready_n,\r
 934 \r
 935         mr_stat_1000base_x_fd,\r
 936         mr_stat_1000base_x_hd,\r
 937         mr_stat_1000base_t_fd,\r
 938         mr_stat_1000base_t_hd,\r
 939 \r
 940         mr_stat_100base_t4,\r
 941         mr_stat_100base_x_fd,\r
 942         mr_stat_100base_x_hd,\r
 943         mr_stat_10mbps_fd,\r
 944         mr_stat_10mbps_hd,\r
 945         mr_stat_100base_t2_fd,\r
 946         mr_stat_100base_t2_hd,\r
 947 \r
 948         mr_stat_extended_stat,\r
 949         mr_stat_unidir_able,\r
 950         mr_stat_preamb_supr,\r
 951         mr_stat_an_complete,\r
 952         mr_stat_remote_fault,\r
 953         mr_stat_an_able,\r
 954         mr_stat_link_stat,\r
 955         mr_stat_jab_det,\r
 956         mr_stat_extended_cap,\r
 957 \r
 958         mr_page_rx,\r
 959         mr_lp_adv_ability,\r
 960 \r
 961         mr_main_reset,\r
 962         mr_loopback_enable,\r
 963         mr_speed_selection,\r
 964         mr_an_enable,\r
 965         mr_power_down,\r
 966         mr_isolate,\r
 967         mr_restart_an,\r
 968         mr_duplex_mode,\r
 969         mr_col_test,\r
 970         mr_unidir_enable,\r
 971         mr_adv_ability\r
 972 );\r
 973 \r
 974 input           rst_n;\r
 975 input           hclk;\r
 976 input           gbe_mode;\r
 977 input           sgmii_mode;\r
 978 input           hcs_n;\r
 979 input           hwrite_n;\r
 980 input    [5:0]  haddr;\r
 981 input    [7:0]  hdatain;\r
 982 \r
 983 output   [7:0]  hdataout;\r
 984 output          hready_n;\r
 985 \r
 986 input           mr_stat_1000base_x_fd;\r
 987 input           mr_stat_1000base_x_hd;\r
 988 input           mr_stat_1000base_t_fd;\r
 989 input           mr_stat_1000base_t_hd;\r
 990 \r
 991 input           mr_stat_100base_t4;\r
 992 input           mr_stat_100base_x_fd;\r
 993 input           mr_stat_100base_x_hd;\r
 994 input           mr_stat_10mbps_fd;\r
 995 input           mr_stat_10mbps_hd;\r
 996 input           mr_stat_100base_t2_fd;\r
 997 input           mr_stat_100base_t2_hd;\r
 998 \r
 999 input           mr_stat_extended_stat;\r
1000 input           mr_stat_unidir_able;\r
1001 input           mr_stat_preamb_supr;\r
1002 input           mr_stat_an_complete;\r
1003 input           mr_stat_remote_fault;\r
1004 input           mr_stat_an_able;\r
1005 input           mr_stat_link_stat;\r
1006 input           mr_stat_jab_det;\r
1007 input           mr_stat_extended_cap;\r
1008 \r
1009 input           mr_page_rx;\r
1010 input    [15:0] mr_lp_adv_ability;\r
1011 \r
1012 output          mr_main_reset;\r
1013 output          mr_loopback_enable;\r
1014 output [1:0]    mr_speed_selection;\r
1015 output          mr_an_enable;\r
1016 output          mr_power_down;\r
1017 output          mr_isolate;\r
1018 output          mr_restart_an;\r
1019 output          mr_duplex_mode;\r
1020 output          mr_col_test;\r
1021 output          mr_unidir_enable;\r
1022 output   [15:0] mr_adv_ability;\r
1023 \r
1024 ///////////////////////////////////\r
1025 \r
1026 \r
1027 \r
1028 reg   [7:0]  hdataout;\r
1029 reg hr;\r
1030 reg hready_n;\r
1031 \r
1032 reg hcs_n_delayed;\r
1033 \r
1034 wire reg0_cs_0;\r
1035 wire reg0_cs_1;\r
1036 \r
1037 wire reg1_cs_0;\r
1038 wire reg1_cs_1;\r
1039 \r
1040 wire reg4_cs_0;\r
1041 wire reg4_cs_1;\r
1042 \r
1043 wire reg5_cs_0;\r
1044 wire reg5_cs_1;\r
1045 \r
1046 wire reg6_cs_0;\r
1047 wire reg6_cs_1;\r
1048 \r
1049 wire regf_cs_0;\r
1050 wire regf_cs_1;\r
1051 \r
1052 wire [15:0] data_out_reg_0;\r
1053 wire [15:0] data_out_reg_1;\r
1054 wire [15:0] data_out_reg_4;\r
1055 wire [15:0] data_out_reg_5;\r
1056 wire [15:0] data_out_reg_6;\r
1057 wire [15:0] data_out_reg_f;\r
1058 \r
1059 \r
1060 \r
1061 register_addr_decoder ad_dec (\r
1062         .rst_n(rst_n),\r
1063         .addr(haddr),\r
1064         .cs_in(~hcs_n),\r
1065 \r
1066         .reg0_cs_0 (reg0_cs_0),\r
1067         .reg0_cs_1 (reg0_cs_1),\r
1068         .reg1_cs_0 (reg1_cs_0),\r
1069         .reg1_cs_1 (reg1_cs_1),\r
1070         .reg4_cs_0 (reg4_cs_0),\r
1071         .reg4_cs_1 (reg4_cs_1),\r
1072         .reg5_cs_0 (reg5_cs_0),\r
1073         .reg5_cs_1 (reg5_cs_1),\r
1074         .reg6_cs_0 (reg6_cs_0),\r
1075         .reg6_cs_1 (reg6_cs_1),\r
1076         .regf_cs_0 (regf_cs_0),\r
1077         .regf_cs_1 (regf_cs_1)\r
1078 );\r
1079 \r
1080 \r
1081 register_0_hb   register_0 (\r
1082         .rst_n (rst_n),\r
1083         .clk (hclk), \r
1084         .gbe_mode (gbe_mode),\r
1085         .cs_0 (reg0_cs_0),\r
1086         .cs_1 (reg0_cs_1),\r
1087         .write (~hwrite_n),\r
1088         .ready (1'b1),\r
1089         .data_in ({hdatain, hdatain}),\r
1090 \r
1091         .data_out (data_out_reg_0),\r
1092         .mr_main_reset (mr_main_reset),\r
1093         .mr_loopback_enable (mr_loopback_enable),\r
1094         .mr_speed_selection (mr_speed_selection),\r
1095         .mr_an_enable (mr_an_enable),\r
1096         .mr_power_down (mr_power_down),\r
1097         .mr_isolate (mr_isolate),\r
1098         .mr_restart_an (mr_restart_an),\r
1099         .mr_duplex_mode (mr_duplex_mode),\r
1100         .mr_col_test (mr_col_test),\r
1101         .mr_unidir_enable (mr_unidir_enable)\r
1102 );\r
1103 \r
1104 \r
1105 register_1_hb   register_1 (\r
1106         .rst_n (rst_n),\r
1107         .clk (hclk), \r
1108         .cs_0 (reg1_cs_0),\r
1109         .cs_1 (reg1_cs_1),\r
1110         .write (~hwrite_n),\r
1111         .ready (1'b1),\r
1112 \r
1113         .mr_stat_100base_t4 (mr_stat_100base_t4),\r
1114         .mr_stat_100base_x_fd (mr_stat_100base_x_fd),\r
1115         .mr_stat_100base_x_hd (mr_stat_100base_x_hd),\r
1116         .mr_stat_10mbps_fd (mr_stat_10mbps_fd),\r
1117         .mr_stat_10mbps_hd (mr_stat_10mbps_hd),\r
1118         .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd),\r
1119         .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd),\r
1120 \r
1121         .mr_stat_extended_stat (mr_stat_extended_stat),\r
1122         .mr_stat_unidir_able (mr_stat_unidir_able),\r
1123         .mr_stat_preamb_supr (mr_stat_preamb_supr),\r
1124         .mr_stat_an_complete (mr_stat_an_complete),\r
1125         .mr_stat_remote_fault (mr_stat_remote_fault),\r
1126         .mr_stat_an_able (mr_stat_an_able),\r
1127         .mr_stat_link_stat (mr_stat_link_stat),\r
1128         .mr_stat_jab_det (mr_stat_jab_det),\r
1129         .mr_stat_extended_cap (mr_stat_extended_cap),\r
1130 \r
1131         .data_out (data_out_reg_1)\r
1132 );\r
1133 \r
1134 \r
1135 register_4_hb   register_4 (\r
1136         .rst_n (rst_n),\r
1137         .clk (hclk), \r
1138         .gbe_mode (gbe_mode),\r
1139         .sgmii_mode (sgmii_mode),\r
1140         .cs_0 (reg4_cs_0),\r
1141         .cs_1 (reg4_cs_1),\r
1142         .write (~hwrite_n),\r
1143         .ready (1'b1),\r
1144         .data_in ({hdatain, hdatain}),\r
1145 \r
1146         .data_out (data_out_reg_4),\r
1147         .mr_adv_ability (mr_adv_ability)\r
1148 );\r
1149 \r
1150 \r
1151 register_5_hb   register_5 (\r
1152         .rst_n (rst_n),\r
1153         .mr_lp_adv_ability (mr_lp_adv_ability),\r
1154         .cs_0 (reg5_cs_0),\r
1155         .cs_1 (reg5_cs_1),\r
1156         .ready (1'b1),\r
1157 \r
1158         .data_out (data_out_reg_5)\r
1159 );\r
1160 \r
1161 \r
1162 register_6_hb   register_6 (\r
1163         .rst_n (rst_n),\r
1164         .clk (hclk), \r
1165         .mr_page_rx (mr_page_rx),\r
1166         .cs_0 (reg6_cs_0),\r
1167         .cs_1 (reg6_cs_1),\r
1168         .write (~hwrite_n),\r
1169         .ready (1'b1),\r
1170 \r
1171         .data_out (data_out_reg_6)\r
1172 );\r
1173 \r
1174 \r
1175 \r
1176 register_f_hb   register_f (\r
1177         .rst_n (rst_n),\r
1178         .cs_0 (regf_cs_0),\r
1179         .cs_1 (regf_cs_1),\r
1180 \r
1181         .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd),\r
1182         .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd),\r
1183         .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd),\r
1184         .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd),\r
1185 \r
1186         .data_out (data_out_reg_f)\r
1187 );\r
1188 \r
1189 \r
1190 // generate an ack\r
1191 always @(posedge hclk or negedge rst_n) begin\r
1192         if (rst_n == 1'b0) begin\r
1193                 hcs_n_delayed <= 1'b1;\r
1194                 hr <= 1'b1;\r
1195                 hready_n <= 1'b1;\r
1196         end\r
1197         else begin\r
1198                 hcs_n_delayed <= hcs_n;\r
1199 \r
1200                 //assert on falling edge of delayed chip select\r
1201                 hr <= ~hcs_n & hcs_n_delayed;\r
1202                 hready_n <= ~hr;\r
1203         end\r
1204 end\r
1205 \r
1206 \r
1207 \r
1208 // Mux Register Read-Data Outputs\r
1209 always @(posedge hclk or negedge rst_n)\r
1210 begin\r
1211         if (rst_n == 1'b0) begin\r
1212                 hdataout <= 8'd0;\r
1213         end\r
1214         else begin\r
1215                 case (haddr[5:0])\r
1216 \r
1217                         6'd0:\r
1218                           begin\r
1219                                 hdataout <= data_out_reg_0[7:0];\r
1220                           end\r
1221 \r
1222 \r
1223                         6'd1:\r
1224                           begin\r
1225                                 hdataout <= data_out_reg_0[15:8];\r
1226                           end\r
1227 \r
1228                         /////////////////////////////////////////////\r
1229 \r
1230                         6'd2:\r
1231                           begin\r
1232                                 hdataout <= data_out_reg_1[7:0];\r
1233                           end\r
1234 \r
1235 \r
1236                         6'd3:\r
1237                           begin\r
1238                                 hdataout <= data_out_reg_1[15:8];\r
1239                           end\r
1240 \r
1241                         /////////////////////////////////////////////\r
1242 \r
1243                         6'd8:\r
1244                           begin\r
1245                                 hdataout <= data_out_reg_4[7:0];\r
1246                           end\r
1247 \r
1248 \r
1249                         6'd9:\r
1250                           begin\r
1251                                 hdataout <= data_out_reg_4[15:8];\r
1252                           end\r
1253 \r
1254                         /////////////////////////////////////////////\r
1255 \r
1256                         6'd10:\r
1257                           begin\r
1258                                 hdataout <= data_out_reg_5[7:0];\r
1259                           end\r
1260 \r
1261 \r
1262                         6'd11:\r
1263                           begin\r
1264                                 hdataout <= data_out_reg_5[15:8];\r
1265                           end\r
1266 \r
1267                         /////////////////////////////////////////////\r
1268 \r
1269                         6'd12:\r
1270                           begin\r
1271                                 hdataout <= data_out_reg_6[7:0];\r
1272                           end\r
1273 \r
1274 \r
1275                         6'd13:\r
1276                           begin\r
1277                                 hdataout <= data_out_reg_6[15:8];\r
1278                           end\r
1279 \r
1280                         /////////////////////////////////////////////\r
1281 \r
1282                         6'd30:\r
1283                           begin\r
1284                                 hdataout <= data_out_reg_f[7:0];\r
1285                           end\r
1286 \r
1287 \r
1288                         6'd31:\r
1289                           begin\r
1290                                 hdataout <= data_out_reg_f[15:8];\r
1291                           end\r
1292 \r
1293                         /////////////////////////////////////////////\r
1294 \r
1295                         default:\r
1296                           begin\r
1297                                 hdataout <= 8'd0;\r
1298                           end\r
1299                 endcase\r
1300         end\r
1301 end\r
1302 \r
1303 endmodule\r
1304 \r
1305 module register_addr_decoder (\r
1306         rst_n,\r
1307         addr,\r
1308         cs_in,\r
1309 \r
1310         reg0_cs_0,\r
1311         reg0_cs_1,\r
1312 \r
1313         reg1_cs_0,\r
1314         reg1_cs_1,\r
1315 \r
1316         reg4_cs_0,\r
1317         reg4_cs_1,\r
1318 \r
1319         reg5_cs_0,\r
1320         reg5_cs_1,\r
1321 \r
1322         reg6_cs_0,\r
1323         reg6_cs_1,\r
1324 \r
1325         regf_cs_0,\r
1326         regf_cs_1\r
1327 );\r
1328 \r
1329 input           rst_n;\r
1330 input           cs_in;\r
1331 input [5:0]     addr;\r
1332 \r
1333 output          reg0_cs_0;\r
1334 output          reg0_cs_1;\r
1335 \r
1336 output          reg1_cs_0;\r
1337 output          reg1_cs_1;\r
1338 \r
1339 output          reg4_cs_0;\r
1340 output          reg4_cs_1;\r
1341 \r
1342 output          reg5_cs_0;\r
1343 output          reg5_cs_1;\r
1344 \r
1345 output          reg6_cs_0;\r
1346 output          reg6_cs_1;\r
1347 \r
1348 output          regf_cs_0;\r
1349 output          regf_cs_1;\r
1350 \r
1351 //////////////////////////\r
1352 \r
1353 wire             reg0_cs_0;\r
1354 wire             reg0_cs_1;\r
1355 \r
1356 wire             reg1_cs_0;\r
1357 wire             reg1_cs_1;\r
1358 \r
1359 wire             reg4_cs_0;\r
1360 wire             reg4_cs_1;\r
1361 \r
1362 wire             reg5_cs_0;\r
1363 wire             reg5_cs_1;\r
1364 \r
1365 wire             reg6_cs_0;\r
1366 wire             reg6_cs_1;\r
1367 \r
1368 wire             regf_cs_0;\r
1369 wire             regf_cs_1;\r
1370 \r
1371 //////////////////////////\r
1372 \r
1373 assign reg0_cs_0 = (addr == 6'h00) ? cs_in : 1'b0;\r
1374 assign reg0_cs_1 = (addr == 6'h01) ? cs_in : 1'b0;\r
1375 \r
1376 assign reg1_cs_0 = (addr == 6'h02) ? cs_in : 1'b0;\r
1377 assign reg1_cs_1 = (addr == 6'h03) ? cs_in : 1'b0;\r
1378 \r
1379 assign reg4_cs_0 = (addr == 6'h08) ? cs_in : 1'b0;\r
1380 assign reg4_cs_1 = (addr == 6'h09) ? cs_in : 1'b0;\r
1381 \r
1382 assign reg5_cs_0 = (addr == 6'h0a) ? cs_in : 1'b0;\r
1383 assign reg5_cs_1 = (addr == 6'h0b) ? cs_in : 1'b0;\r
1384 \r
1385 assign reg6_cs_0 = (addr == 6'h0c) ? cs_in : 1'b0;\r
1386 assign reg6_cs_1 = (addr == 6'h0d) ? cs_in : 1'b0;\r
1387 \r
1388 assign regf_cs_0 = (addr == 6'h1e) ? cs_in : 1'b0;\r
1389 assign regf_cs_1 = (addr == 6'h1f) ? cs_in : 1'b0;\r
1390 \r
1391 \r
1392 endmodule\r
1393 \r