1 @W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
2 @W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
3 @W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
4 @W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
jspc29 / trb5sc.git / blob