jspc29.x-matter.uni-frankfurt.de Git - trb5sc.git/blob

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <BaliProject version="3.2" title="sgmii_channel_smi_reference_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="sgmii_channel_smi_reference_eval_hb">
   3     <Implementation title="sgmii_channel_smi_reference_eval_hb" dir="sgmii_channel_smi_reference_eval_hb" description="sgmii_channel_smi_reference_eval_hb" default_strategy="sgmii_channel_smi_reference_eval">
   4         <Options>
   5             <Option name="top" value="top_hb"/>
   6         </Options>
   7 <Source name="../../../src/rtl/template/ecp5um/register_interface_hb.v" type="Verilog"/>
   8 <Source name="../../../src/rtl/template/ecp5um/rate_resolution.v" type="Verilog"/>
   9 <Source name="../../../../../sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v" type="Verilog"/>
  10 <Source name="../../../../../sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v" type="Verilog"/>
  11 <Source name="../../../../../sgmii_channel_smi.vhd" type="VHDL"/>
  12 <Source name="../../../src/rtl/top/ecp5um/top_hb.v" type="Verilog"/>
  13         <Source name="sgmii_channel_smi_reference_eval.lpf" type="Logic Preference"/>
  14     </Implementation>
  15  <Strategy name="sgmii_channel_smi_reference_eval" file="sgmii_channel_smi_reference_eval.sty"/>
  16 </BaliProject>