1 @N: MF248 |Running in 64-bit mode.
2 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
3 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0]
4 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0]
5 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0]
6 @N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
7 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0]
8 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0]
9 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0]
10 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0]
11 @N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0]
12 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
13 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
14 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
15 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
16 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
17 @N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
18 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
19 @N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
20 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
21 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
22 @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
23 @N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
jspc29 / trb5sc.git / blob