1 @N|Running in 64-bit mode
2 @N|Running in 64-bit mode
3 @N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
4 @N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
5 @N|Running in 64-bit mode
6 @N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
7 @N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
8 @N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
9 @N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
10 @N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
11 @N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
12 @N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
13 @N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
14 @N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
15 @N|Running in 64-bit mode
jspc29 / trb5sc.git / blob