1 <?xml version="1.0" encoding="UTF-8" ?>
2 <!-- *************************************************************************************
4 Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
5 *******************************************************************************************-->
6 <report_table display_priority="2" name="Timing Summary">
7 <report_link name="Detailed report">
8 <data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr</data>
9 <title>START OF TIMING REPORT</title>
12 <data tcl_name="clock_name">Clock Name</data>
13 <data tcl_name="req_freq">Req Freq</data>
14 <data tcl_name="est_freq">Est Freq</data>
15 <data tcl_name="slack">Slack</data>
19 <data>100.0 MHz</data>