1 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
2 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
3 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
4 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
5 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
6 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
7 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
8 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
9 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
10 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
11 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
12 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
13 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
14 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
15 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
16 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
17 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
18 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
19 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
20 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
21 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
22 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
23 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
24 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
25 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
26 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
27 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
28 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
29 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
30 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
31 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
32 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
33 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
34 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
35 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
36 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
37 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
38 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
39 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
40 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
41 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
42 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
43 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
44 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
45 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
46 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
47 @W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
48 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
49 @W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
50 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
51 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
52 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
53 @W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
54 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
55 @W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
56 @W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
57 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
58 @W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
59 @W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
60 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
61 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
62 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
63 @W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
64 @W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
65 @W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
66 @W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
67 @W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
68 @W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
69 @W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
70 @W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
71 @W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
72 @W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
73 @W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
74 @W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
75 @W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
76 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
77 @W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
jspc29 / trb5sc.git / blob