jspc29.x-matter.uni-frankfurt.de Git - mvd_firmware.git/blob

   1 ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************\r
   2 ;* File Name          : startup_stm32f10x_cl.s\r
   3 ;* Author             : MCD Application Team\r
   4 ;* Version            : V3.5.0\r
   5 ;* Date               : 11-March-2011\r
   6 ;* Description        : STM32F10x Connectivity line devices vector table for MDK-ARM \r
   7 ;*                      toolchain. \r
   8 ;*                      This module performs:\r
   9 ;*                      - Set the initial SP\r
  10 ;*                      - Set the initial PC == Reset_Handler\r
  11 ;*                      - Set the vector table entries with the exceptions ISR address\r
  12 ;*                      - Configure the clock system\r
  13 ;*                      - Branches to __main in the C library (which eventually\r
  14 ;*                        calls main()).\r
  15 ;*                      After Reset the CortexM3 processor is in Thread mode,\r
  16 ;*                      priority is Privileged, and the Stack is set to Main.\r
  17 ;* <<< Use Configuration Wizard in Context Menu >>>   \r
  18 ;*******************************************************************************\r
  19 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  20 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
  21 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
  22 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
  23 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
  24 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  25 ;*******************************************************************************\r
  26 \r
  27 ; Amount of memory (in bytes) allocated for Stack\r
  28 ; Tailor this value to your application needs\r
  29 ; <h> Stack Configuration\r
  30 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  31 ; </h>\r
  32 \r
  33 Stack_Size      EQU     0x00000400\r
  34 \r
  35                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  36 Stack_Mem       SPACE   Stack_Size\r
  37 __initial_sp\r
  38 \r
  39 \r
  40 ; <h> Heap Configuration\r
  41 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  42 ; </h>\r
  43 \r
  44 Heap_Size       EQU     0x00000200\r
  45 \r
  46                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  47 __heap_base\r
  48 Heap_Mem        SPACE   Heap_Size\r
  49 __heap_limit\r
  50 \r
  51                 PRESERVE8\r
  52                 THUMB\r
  53 \r
  54 \r
  55 ; Vector Table Mapped to Address 0 at Reset\r
  56                 AREA    RESET, DATA, READONLY\r
  57                 EXPORT  __Vectors\r
  58                 EXPORT  __Vectors_End\r
  59                 EXPORT  __Vectors_Size\r
  60 \r
  61 __Vectors       DCD     __initial_sp               ; Top of Stack\r
  62                 DCD     Reset_Handler              ; Reset Handler\r
  63                 DCD     NMI_Handler                ; NMI Handler\r
  64                 DCD     HardFault_Handler          ; Hard Fault Handler\r
  65                 DCD     MemManage_Handler          ; MPU Fault Handler\r
  66                 DCD     BusFault_Handler           ; Bus Fault Handler\r
  67                 DCD     UsageFault_Handler         ; Usage Fault Handler\r
  68                 DCD     0                          ; Reserved\r
  69                 DCD     0                          ; Reserved\r
  70                 DCD     0                          ; Reserved\r
  71                 DCD     0                          ; Reserved\r
  72                 DCD     SVC_Handler                ; SVCall Handler\r
  73                 DCD     DebugMon_Handler           ; Debug Monitor Handler\r
  74                 DCD     0                          ; Reserved\r
  75                 DCD     PendSV_Handler             ; PendSV Handler\r
  76                 DCD     SysTick_Handler            ; SysTick Handler\r
  77 \r
  78                 ; External Interrupts\r
  79                 DCD     WWDG_IRQHandler            ; Window Watchdog\r
  80                 DCD     PVD_IRQHandler             ; PVD through EXTI Line detect\r
  81                 DCD     TAMPER_IRQHandler          ; Tamper\r
  82                 DCD     RTC_IRQHandler             ; RTC\r
  83                 DCD     FLASH_IRQHandler           ; Flash\r
  84                 DCD     RCC_IRQHandler             ; RCC\r
  85                 DCD     EXTI0_IRQHandler           ; EXTI Line 0\r
  86                 DCD     EXTI1_IRQHandler           ; EXTI Line 1\r
  87                 DCD     EXTI2_IRQHandler           ; EXTI Line 2\r
  88                 DCD     EXTI3_IRQHandler           ; EXTI Line 3\r
  89                 DCD     EXTI4_IRQHandler           ; EXTI Line 4\r
  90                 DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1\r
  91                 DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2\r
  92                 DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3\r
  93                 DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4\r
  94                 DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5\r
  95                 DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6\r
  96                 DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7\r
  97                 DCD     ADC1_2_IRQHandler          ; ADC1 and ADC2\r
  98                 DCD     CAN1_TX_IRQHandler         ; CAN1 TX\r
  99                 DCD     CAN1_RX0_IRQHandler        ; CAN1 RX0\r
 100                 DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1\r
 101                 DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE\r
 102                 DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5\r
 103                 DCD     TIM1_BRK_IRQHandler        ; TIM1 Break\r
 104                 DCD     TIM1_UP_IRQHandler         ; TIM1 Update\r
 105                 DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation\r
 106                 DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare\r
 107                 DCD     TIM2_IRQHandler            ; TIM2\r
 108                 DCD     TIM3_IRQHandler            ; TIM3\r
 109                 DCD     TIM4_IRQHandler            ; TIM4\r
 110                 DCD     I2C1_EV_IRQHandler         ; I2C1 Event\r
 111                 DCD     I2C1_ER_IRQHandler         ; I2C1 Error\r
 112                 DCD     I2C2_EV_IRQHandler         ; I2C2 Event\r
 113                 DCD     I2C2_ER_IRQHandler         ; I2C1 Error\r
 114                 DCD     SPI1_IRQHandler            ; SPI1\r
 115                 DCD     SPI2_IRQHandler            ; SPI2\r
 116                 DCD     USART1_IRQHandler          ; USART1\r
 117                 DCD     USART2_IRQHandler          ; USART2\r
 118                 DCD     USART3_IRQHandler          ; USART3\r
 119                 DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10\r
 120                 DCD     RTCAlarm_IRQHandler        ; RTC alarm through EXTI line\r
 121                 DCD     OTG_FS_WKUP_IRQHandler     ; USB OTG FS Wakeup through EXTI line\r
 122                 DCD     0                          ; Reserved\r
 123                 DCD     0                          ; Reserved\r
 124                 DCD     0                          ; Reserved\r
 125                 DCD     0                          ; Reserved\r
 126                 DCD     0                          ; Reserved\r
 127                 DCD     0                          ; Reserved\r
 128                 DCD     0                          ; Reserved\r
 129                 DCD     TIM5_IRQHandler            ; TIM5\r
 130                 DCD     SPI3_IRQHandler            ; SPI3\r
 131                 DCD     UART4_IRQHandler           ; UART4\r
 132                 DCD     UART5_IRQHandler           ; UART5\r
 133                 DCD     TIM6_IRQHandler            ; TIM6\r
 134                 DCD     TIM7_IRQHandler            ; TIM7\r
 135                 DCD     DMA2_Channel1_IRQHandler   ; DMA2 Channel1\r
 136                 DCD     DMA2_Channel2_IRQHandler   ; DMA2 Channel2\r
 137                 DCD     DMA2_Channel3_IRQHandler   ; DMA2 Channel3\r
 138                 DCD     DMA2_Channel4_IRQHandler   ; DMA2 Channel4\r
 139                 DCD     DMA2_Channel5_IRQHandler   ; DMA2 Channel5\r
 140                 DCD     ETH_IRQHandler             ; Ethernet\r
 141                 DCD     ETH_WKUP_IRQHandler        ; Ethernet Wakeup through EXTI line\r
 142                 DCD     CAN2_TX_IRQHandler         ; CAN2 TX\r
 143                 DCD     CAN2_RX0_IRQHandler        ; CAN2 RX0\r
 144                 DCD     CAN2_RX1_IRQHandler        ; CAN2 RX1\r
 145                 DCD     CAN2_SCE_IRQHandler        ; CAN2 SCE\r
 146                 DCD     OTG_FS_IRQHandler          ; USB OTG FS\r
 147 __Vectors_End\r
 148 \r
 149 __Vectors_Size  EQU  __Vectors_End - __Vectors\r
 150 \r
 151                 AREA    |.text|, CODE, READONLY\r
 152 \r
 153 ; Reset handler\r
 154 Reset_Handler    PROC\r
 155                  EXPORT  Reset_Handler             [WEAK]\r
 156         IMPORT  SystemInit\r
 157         IMPORT  __main\r
 158                  LDR     R0, =SystemInit\r
 159                  BLX     R0\r
 160                  LDR     R0, =__main\r
 161                  BX      R0\r
 162                  ENDP\r
 163 \r
 164 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 165 \r
 166 NMI_Handler     PROC\r
 167                 EXPORT  NMI_Handler                [WEAK]\r
 168                 B       .\r
 169                 ENDP\r
 170 HardFault_Handler\\r
 171                 PROC\r
 172                 EXPORT  HardFault_Handler          [WEAK]\r
 173                 B       .\r
 174                 ENDP\r
 175 MemManage_Handler\\r
 176                 PROC\r
 177                 EXPORT  MemManage_Handler          [WEAK]\r
 178                 B       .\r
 179                 ENDP\r
 180 BusFault_Handler\\r
 181                 PROC\r
 182                 EXPORT  BusFault_Handler           [WEAK]\r
 183                 B       .\r
 184                 ENDP\r
 185 UsageFault_Handler\\r
 186                 PROC\r
 187                 EXPORT  UsageFault_Handler         [WEAK]\r
 188                 B       .\r
 189                 ENDP\r
 190 SVC_Handler     PROC\r
 191                 EXPORT  SVC_Handler                [WEAK]\r
 192                 B       .\r
 193                 ENDP\r
 194 DebugMon_Handler\\r
 195                 PROC\r
 196                 EXPORT  DebugMon_Handler           [WEAK]\r
 197                 B       .\r
 198                 ENDP\r
 199 PendSV_Handler  PROC\r
 200                 EXPORT  PendSV_Handler             [WEAK]\r
 201                 B       .\r
 202                 ENDP\r
 203 SysTick_Handler PROC\r
 204                 EXPORT  SysTick_Handler            [WEAK]\r
 205                 B       .\r
 206                 ENDP\r
 207 \r
 208 Default_Handler PROC\r
 209 \r
 210                 EXPORT  WWDG_IRQHandler            [WEAK]\r
 211                 EXPORT  PVD_IRQHandler             [WEAK]\r
 212                 EXPORT  TAMPER_IRQHandler          [WEAK]\r
 213                 EXPORT  RTC_IRQHandler             [WEAK]\r
 214                 EXPORT  FLASH_IRQHandler           [WEAK]\r
 215                 EXPORT  RCC_IRQHandler             [WEAK]\r
 216                 EXPORT  EXTI0_IRQHandler           [WEAK]\r
 217                 EXPORT  EXTI1_IRQHandler           [WEAK]\r
 218                 EXPORT  EXTI2_IRQHandler           [WEAK]\r
 219                 EXPORT  EXTI3_IRQHandler           [WEAK]\r
 220                 EXPORT  EXTI4_IRQHandler           [WEAK]\r
 221                 EXPORT  DMA1_Channel1_IRQHandler   [WEAK]\r
 222                 EXPORT  DMA1_Channel2_IRQHandler   [WEAK]\r
 223                 EXPORT  DMA1_Channel3_IRQHandler   [WEAK]\r
 224                 EXPORT  DMA1_Channel4_IRQHandler   [WEAK]\r
 225                 EXPORT  DMA1_Channel5_IRQHandler   [WEAK]\r
 226                 EXPORT  DMA1_Channel6_IRQHandler   [WEAK]\r
 227                 EXPORT  DMA1_Channel7_IRQHandler   [WEAK]\r
 228                 EXPORT  ADC1_2_IRQHandler          [WEAK]\r
 229                 EXPORT  CAN1_TX_IRQHandler         [WEAK]\r
 230                 EXPORT  CAN1_RX0_IRQHandler        [WEAK]\r
 231                 EXPORT  CAN1_RX1_IRQHandler        [WEAK]\r
 232                 EXPORT  CAN1_SCE_IRQHandler        [WEAK]\r
 233                 EXPORT  EXTI9_5_IRQHandler         [WEAK]\r
 234                 EXPORT  TIM1_BRK_IRQHandler        [WEAK]\r
 235                 EXPORT  TIM1_UP_IRQHandler         [WEAK]\r
 236                 EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]\r
 237                 EXPORT  TIM1_CC_IRQHandler         [WEAK]\r
 238                 EXPORT  TIM2_IRQHandler            [WEAK]\r
 239                 EXPORT  TIM3_IRQHandler            [WEAK]\r
 240                 EXPORT  TIM4_IRQHandler            [WEAK]\r
 241                 EXPORT  I2C1_EV_IRQHandler         [WEAK]\r
 242                 EXPORT  I2C1_ER_IRQHandler         [WEAK]\r
 243                 EXPORT  I2C2_EV_IRQHandler         [WEAK]\r
 244                 EXPORT  I2C2_ER_IRQHandler         [WEAK]\r
 245                 EXPORT  SPI1_IRQHandler            [WEAK]\r
 246                 EXPORT  SPI2_IRQHandler            [WEAK]\r
 247                 EXPORT  USART1_IRQHandler          [WEAK]\r
 248                 EXPORT  USART2_IRQHandler          [WEAK]\r
 249                 EXPORT  USART3_IRQHandler          [WEAK]\r
 250                 EXPORT  EXTI15_10_IRQHandler       [WEAK]\r
 251                 EXPORT  RTCAlarm_IRQHandler        [WEAK]\r
 252                 EXPORT  OTG_FS_WKUP_IRQHandler     [WEAK]\r
 253                 EXPORT  TIM5_IRQHandler            [WEAK]\r
 254                 EXPORT  SPI3_IRQHandler            [WEAK]\r
 255                 EXPORT  UART4_IRQHandler           [WEAK]\r
 256                 EXPORT  UART5_IRQHandler           [WEAK]\r
 257                 EXPORT  TIM6_IRQHandler            [WEAK]\r
 258                 EXPORT  TIM7_IRQHandler            [WEAK]\r
 259                 EXPORT  DMA2_Channel1_IRQHandler   [WEAK]\r
 260                 EXPORT  DMA2_Channel2_IRQHandler   [WEAK]\r
 261                 EXPORT  DMA2_Channel3_IRQHandler   [WEAK]\r
 262                 EXPORT  DMA2_Channel4_IRQHandler   [WEAK]\r
 263                 EXPORT  DMA2_Channel5_IRQHandler   [WEAK]\r
 264                 EXPORT  ETH_IRQHandler             [WEAK]\r
 265                 EXPORT  ETH_WKUP_IRQHandler        [WEAK]\r
 266                 EXPORT  CAN2_TX_IRQHandler         [WEAK]\r
 267                 EXPORT  CAN2_RX0_IRQHandler        [WEAK]\r
 268                 EXPORT  CAN2_RX1_IRQHandler        [WEAK]\r
 269                 EXPORT  CAN2_SCE_IRQHandler        [WEAK]\r
 270                 EXPORT  OTG_FS_IRQHandler          [WEAK]\r
 271 \r
 272 WWDG_IRQHandler\r
 273 PVD_IRQHandler\r
 274 TAMPER_IRQHandler\r
 275 RTC_IRQHandler\r
 276 FLASH_IRQHandler\r
 277 RCC_IRQHandler\r
 278 EXTI0_IRQHandler\r
 279 EXTI1_IRQHandler\r
 280 EXTI2_IRQHandler\r
 281 EXTI3_IRQHandler\r
 282 EXTI4_IRQHandler\r
 283 DMA1_Channel1_IRQHandler\r
 284 DMA1_Channel2_IRQHandler\r
 285 DMA1_Channel3_IRQHandler\r
 286 DMA1_Channel4_IRQHandler\r
 287 DMA1_Channel5_IRQHandler\r
 288 DMA1_Channel6_IRQHandler\r
 289 DMA1_Channel7_IRQHandler\r
 290 ADC1_2_IRQHandler\r
 291 CAN1_TX_IRQHandler\r
 292 CAN1_RX0_IRQHandler\r
 293 CAN1_RX1_IRQHandler\r
 294 CAN1_SCE_IRQHandler\r
 295 EXTI9_5_IRQHandler\r
 296 TIM1_BRK_IRQHandler\r
 297 TIM1_UP_IRQHandler\r
 298 TIM1_TRG_COM_IRQHandler\r
 299 TIM1_CC_IRQHandler\r
 300 TIM2_IRQHandler\r
 301 TIM3_IRQHandler\r
 302 TIM4_IRQHandler\r
 303 I2C1_EV_IRQHandler\r
 304 I2C1_ER_IRQHandler\r
 305 I2C2_EV_IRQHandler\r
 306 I2C2_ER_IRQHandler\r
 307 SPI1_IRQHandler\r
 308 SPI2_IRQHandler\r
 309 USART1_IRQHandler\r
 310 USART2_IRQHandler\r
 311 USART3_IRQHandler\r
 312 EXTI15_10_IRQHandler\r
 313 RTCAlarm_IRQHandler\r
 314 OTG_FS_WKUP_IRQHandler\r
 315 TIM5_IRQHandler\r
 316 SPI3_IRQHandler\r
 317 UART4_IRQHandler\r
 318 UART5_IRQHandler\r
 319 TIM6_IRQHandler\r
 320 TIM7_IRQHandler\r
 321 DMA2_Channel1_IRQHandler\r
 322 DMA2_Channel2_IRQHandler\r
 323 DMA2_Channel3_IRQHandler\r
 324 DMA2_Channel4_IRQHandler\r
 325 DMA2_Channel5_IRQHandler\r
 326 ETH_IRQHandler\r
 327 ETH_WKUP_IRQHandler\r
 328 CAN2_TX_IRQHandler\r
 329 CAN2_RX0_IRQHandler\r
 330 CAN2_RX1_IRQHandler\r
 331 CAN2_SCE_IRQHandler\r
 332 OTG_FS_IRQHandler\r
 333 \r
 334                 B       .\r
 335 \r
 336                 ENDP\r
 337 \r
 338                 ALIGN\r
 339 \r
 340 ;*******************************************************************************\r
 341 ; User Stack and Heap initialization\r
 342 ;*******************************************************************************\r
 343                  IF      :DEF:__MICROLIB\r
 344                 \r
 345                  EXPORT  __initial_sp\r
 346                  EXPORT  __heap_base\r
 347                  EXPORT  __heap_limit\r
 348                 \r
 349                  ELSE\r
 350                 \r
 351                  IMPORT  __use_two_region_memory\r
 352                  EXPORT  __user_initial_stackheap\r
 353                  \r
 354 __user_initial_stackheap\r
 355 \r
 356                  LDR     R0, =  Heap_Mem\r
 357                  LDR     R1, =(Stack_Mem + Stack_Size)\r
 358                  LDR     R2, = (Heap_Mem +  Heap_Size)\r
 359                  LDR     R3, = Stack_Mem\r
 360                  BX      LR\r
 361 \r
 362                  ALIGN\r
 363 \r
 364                  ENDIF\r
 365 \r
 366                  END\r
 367 \r
 368 ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****\r