1 <?xml version="1.0" encoding="UTF-8" ?>
2 <!-- *************************************************************************************
4 Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
5 *******************************************************************************************-->
6 <report_table display_priority="2" name="Timing Summary">
7 <report_link name="Detailed report">
8 <data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
9 <title>START OF TIMING REPORT</title>
12 <data tcl_name="clock_name">Clock Name</data>
13 <data tcl_name="req_freq">Req Freq</data>
14 <data tcl_name="est_freq">Est Freq</data>
15 <data tcl_name="slack">Slack</data>
18 <data>sgmii_ecp5|pll_refclki</data>
19 <data>100.0 MHz</data>
20 <data>168.9 MHz</data>
24 <data>sgmii_ecp5|rxrefclk</data>
25 <data>100.0 MHz</data>
26 <data>167.9 MHz</data>
30 <data>sgmii_ecp5|tx_pclk_inferred_clock</data>
31 <data>100.0 MHz</data>
32 <data>237.5 MHz</data>
37 <data>100.0 MHz</data>
38 <data>840.7 MHz</data>