1 @N: MF248 |Running in 64-bit mode.
2 @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
3 @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
4 @N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
5 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
6 @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
7 @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
8 @N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
jspc29 / trb5sc.git / blob