1 @W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
2 @W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
3 @W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
jspc29 / trb5sc.git / blob