1 <?xml version="1.0" encoding="UTF-8" ?>
2 <!-- *************************************************************************************
4 The file contains the optimization information from mapper to be displayed as part of the summary report.
5 *******************************************************************************************-->
6 <report_table display_priority="3" name="Optimizations Summary">
7 <parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
9 <report_link name="more">
10 <data>/home/cugur/Projects/TDC_on_TRB3/trb3/base/cores/ecp5/PLL/pll_in200_out100/syn_results/synlog/report/pll_in200_out100_fpga_mapper_combined_clk.rpt</data>
11 <title>START OF CLOCK OPTIMIZATION REPORT</title>