jspc29.x-matter.uni-frankfurt.de Git - trb5sc.git/blob

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <BaliProject version="3.2" title="sgmii_channel_smi_core_only_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="sgmii_channel_smi_top_pcs_core_only">
   3     <Implementation title="sgmii_channel_smi_top_pcs_core_only" dir="sgmii_channel_smi_top_pcs_core_only" description="sgmii_channel_smi_top_pcs_core_only" default_strategy="sgmii_channel_smi_core_only_eval">
   4         <Options>
   5      <Option name="top" value="top_pcs_core_only"/>
   6      </Options>
   7 <Source name="../../../../../sgmii_channel_smi_core_bb.v" type="Verilog"/>
   8 <Source name="../../../src/rtl/top/ecp5um/top_pcs_core_only.v" type="Verilog"/>
   9         <Source name="sgmii_channel_smi_core_only_eval.lpf" type="Logic Preference"/>
  10     </Implementation>
  11     <Strategy name="sgmii_channel_smi_core_only_eval" file="sgmii_channel_smi_core_only_eval.sty"/>
  12 </BaliProject>