jspc29.x-matter.uni-frankfurt.de Git - mvd_firmware.git/blob

   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32f10x_fsmc.c\r
   4   * @author  MCD Application Team\r
   5   * @version V3.5.0\r
   6   * @date    11-March-2011\r
   7   * @brief   This file provides all the FSMC firmware functions.\r
   8   ******************************************************************************\r
   9   * @attention\r
  10   *\r
  11   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  12   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
  13   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
  14   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
  15   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
  16   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  17   *\r
  18   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>\r
  19   ******************************************************************************\r
  20   */\r
  21 \r
  22 /* Includes ------------------------------------------------------------------*/\r
  23 #include "stm32f10x_fsmc.h"\r
  24 #include "stm32f10x_rcc.h"\r
  25 \r
  26 /** @addtogroup STM32F10x_StdPeriph_Driver\r
  27   * @{\r
  28   */\r
  29 \r
  30 /** @defgroup FSMC \r
  31   * @brief FSMC driver modules\r
  32   * @{\r
  33   */ \r
  34 \r
  35 /** @defgroup FSMC_Private_TypesDefinitions\r
  36   * @{\r
  37   */ \r
  38 /**\r
  39   * @}\r
  40   */\r
  41 \r
  42 /** @defgroup FSMC_Private_Defines\r
  43   * @{\r
  44   */\r
  45 \r
  46 /* --------------------- FSMC registers bit mask ---------------------------- */\r
  47 \r
  48 /* FSMC BCRx Mask */\r
  49 #define BCR_MBKEN_Set                       ((uint32_t)0x00000001)\r
  50 #define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)\r
  51 #define BCR_FACCEN_Set                      ((uint32_t)0x00000040)\r
  52 \r
  53 /* FSMC PCRx Mask */\r
  54 #define PCR_PBKEN_Set                       ((uint32_t)0x00000004)\r
  55 #define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)\r
  56 #define PCR_ECCEN_Set                       ((uint32_t)0x00000040)\r
  57 #define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)\r
  58 #define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)\r
  59 /**\r
  60   * @}\r
  61   */\r
  62 \r
  63 /** @defgroup FSMC_Private_Macros\r
  64   * @{\r
  65   */\r
  66 \r
  67 /**\r
  68   * @}\r
  69   */\r
  70 \r
  71 /** @defgroup FSMC_Private_Variables\r
  72   * @{\r
  73   */\r
  74 \r
  75 /**\r
  76   * @}\r
  77   */\r
  78 \r
  79 /** @defgroup FSMC_Private_FunctionPrototypes\r
  80   * @{\r
  81   */\r
  82 \r
  83 /**\r
  84   * @}\r
  85   */\r
  86 \r
  87 /** @defgroup FSMC_Private_Functions\r
  88   * @{\r
  89   */\r
  90 \r
  91 /**\r
  92   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
  93   *         reset values.\r
  94   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
  95   *   This parameter can be one of the following values:\r
  96   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
  97   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
  98   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
  99   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 100   * @retval None\r
 101   */\r
 102 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
 103 {\r
 104   /* Check the parameter */\r
 105   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 106   \r
 107   /* FSMC_Bank1_NORSRAM1 */\r
 108   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
 109   {\r
 110     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    \r
 111   }\r
 112   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
 113   else\r
 114   {   \r
 115     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
 116   }\r
 117   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
 118   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  \r
 119 }\r
 120 \r
 121 /**\r
 122   * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.\r
 123   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 124   *   This parameter can be one of the following values:\r
 125   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 126   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
 127   * @retval None\r
 128   */\r
 129 void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
 130 {\r
 131   /* Check the parameter */\r
 132   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 133   \r
 134   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 135   {\r
 136     /* Set the FSMC_Bank2 registers to their reset values */\r
 137     FSMC_Bank2->PCR2 = 0x00000018;\r
 138     FSMC_Bank2->SR2 = 0x00000040;\r
 139     FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
 140     FSMC_Bank2->PATT2 = 0xFCFCFCFC;  \r
 141   }\r
 142   /* FSMC_Bank3_NAND */  \r
 143   else\r
 144   {\r
 145     /* Set the FSMC_Bank3 registers to their reset values */\r
 146     FSMC_Bank3->PCR3 = 0x00000018;\r
 147     FSMC_Bank3->SR3 = 0x00000040;\r
 148     FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
 149     FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
 150   }  \r
 151 }\r
 152 \r
 153 /**\r
 154   * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
 155   * @param  None                       \r
 156   * @retval None\r
 157   */\r
 158 void FSMC_PCCARDDeInit(void)\r
 159 {\r
 160   /* Set the FSMC_Bank4 registers to their reset values */\r
 161   FSMC_Bank4->PCR4 = 0x00000018; \r
 162   FSMC_Bank4->SR4 = 0x00000000; \r
 163   FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
 164   FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
 165   FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
 166 }\r
 167 \r
 168 /**\r
 169   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified\r
 170   *         parameters in the FSMC_NORSRAMInitStruct.\r
 171   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
 172   *         structure that contains the configuration information for \r
 173   *        the FSMC NOR/SRAM specified Banks.                       \r
 174   * @retval None\r
 175   */\r
 176 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 177 { \r
 178   /* Check the parameters */\r
 179   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
 180   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
 181   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
 182   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
 183   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
 184   assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
 185   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
 186   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
 187   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
 188   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
 189   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
 190   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
 191   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  \r
 192   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
 193   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
 194   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
 195   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
 196   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
 197   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
 198   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
 199   \r
 200   /* Bank1 NOR/SRAM control register configuration */ \r
 201   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 202             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
 203             FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
 204             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
 205             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
 206             FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
 207             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
 208             FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
 209             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
 210             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
 211             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
 212             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
 213             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
 214 \r
 215   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
 216   {\r
 217     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
 218   }\r
 219   \r
 220   /* Bank1 NOR/SRAM timing register configuration */\r
 221   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
 222             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
 223             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
 224             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 225             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
 226             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
 227             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
 228              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
 229             \r
 230     \r
 231   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
 232   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
 233   {\r
 234     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
 235     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
 236     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
 237     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
 238     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
 239     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
 240     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 241               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
 242               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
 243               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 244               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
 245               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
 246                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
 247   }\r
 248   else\r
 249   {\r
 250     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
 251   }\r
 252 }\r
 253 \r
 254 /**\r
 255   * @brief  Initializes the FSMC NAND Banks according to the specified \r
 256   *         parameters in the FSMC_NANDInitStruct.\r
 257   * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
 258   *         structure that contains the configuration information for the FSMC \r
 259   *         NAND specified Banks.                       \r
 260   * @retval None\r
 261   */\r
 262 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 263 {\r
 264   uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
 265     \r
 266   /* Check the parameters */\r
 267   assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
 268   assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
 269   assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
 270   assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
 271   assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
 272   assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
 273   assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
 274   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 275   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 276   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 277   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 278   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 279   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 280   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 281   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 282   \r
 283   /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
 284   tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
 285             PCR_MemoryType_NAND |\r
 286             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
 287             FSMC_NANDInitStruct->FSMC_ECC |\r
 288             FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
 289             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
 290             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
 291             \r
 292   /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
 293   tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 294             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 295             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 296             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 297             \r
 298   /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 299   tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 300             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 301             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 302             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
 303   \r
 304   if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
 305   {\r
 306     /* FSMC_Bank2_NAND registers configuration */\r
 307     FSMC_Bank2->PCR2 = tmppcr;\r
 308     FSMC_Bank2->PMEM2 = tmppmem;\r
 309     FSMC_Bank2->PATT2 = tmppatt;\r
 310   }\r
 311   else\r
 312   {\r
 313     /* FSMC_Bank3_NAND registers configuration */\r
 314     FSMC_Bank3->PCR3 = tmppcr;\r
 315     FSMC_Bank3->PMEM3 = tmppmem;\r
 316     FSMC_Bank3->PATT3 = tmppatt;\r
 317   }\r
 318 }\r
 319 \r
 320 /**\r
 321   * @brief  Initializes the FSMC PCCARD Bank according to the specified \r
 322   *         parameters in the FSMC_PCCARDInitStruct.\r
 323   * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
 324   *         structure that contains the configuration information for the FSMC \r
 325   *         PCCARD Bank.                       \r
 326   * @retval None\r
 327   */\r
 328 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 329 {\r
 330   /* Check the parameters */\r
 331   assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
 332   assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
 333   assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
 334  \r
 335   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 336   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 337   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 338   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 339   \r
 340   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 341   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 342   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 343   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 344   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
 345   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
 346   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
 347   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
 348   \r
 349   /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
 350   FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
 351                      FSMC_MemoryDataWidth_16b |  \r
 352                      (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
 353                      (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
 354             \r
 355   /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
 356   FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 357                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 358                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 359                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 360             \r
 361   /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 362   FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 363                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 364                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 365                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);        \r
 366             \r
 367   /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
 368   FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
 369                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 370                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 371                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             \r
 372 }\r
 373 \r
 374 /**\r
 375   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.\r
 376   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
 377   *         structure which will be initialized.\r
 378   * @retval None\r
 379   */\r
 380 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 381 {  \r
 382   /* Reset NOR/SRAM Init structure parameters values */\r
 383   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
 384   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
 385   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
 386   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 387   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
 388   FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
 389   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
 390   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
 391   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
 392   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
 393   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
 394   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
 395   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
 396   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 397   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 398   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 399   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 400   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 401   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
 402   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
 403   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 404   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 405   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 406   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 407   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 408   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
 409   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
 410 }\r
 411 \r
 412 /**\r
 413   * @brief  Fills each FSMC_NANDInitStruct member with its default value.\r
 414   * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
 415   *         structure which will be initialized.\r
 416   * @retval None\r
 417   */\r
 418 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 419 { \r
 420   /* Reset NAND Init structure parameters values */\r
 421   FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
 422   FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 423   FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 424   FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
 425   FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
 426   FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 427   FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
 428   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 429   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 430   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 431   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 432   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 433   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 434   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 435   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;         \r
 436 }\r
 437 \r
 438 /**\r
 439   * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.\r
 440   * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
 441   *         structure which will be initialized.\r
 442   * @retval None\r
 443   */\r
 444 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 445 {\r
 446   /* Reset PCCARD Init structure parameters values */\r
 447   FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 448   FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 449   FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
 450   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 451   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 452   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 453   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 454   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 455   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 456   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 457   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;     \r
 458   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 459   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 460   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 461   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 462 }\r
 463 \r
 464 /**\r
 465   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.\r
 466   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 467   *   This parameter can be one of the following values:\r
 468   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
 469   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
 470   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
 471   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 472   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
 473   * @retval None\r
 474   */\r
 475 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 476 {\r
 477   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 478   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 479   \r
 480   if (NewState != DISABLE)\r
 481   {\r
 482     /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
 483     FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
 484   }\r
 485   else\r
 486   {\r
 487     /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
 488     FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
 489   }\r
 490 }\r
 491 \r
 492 /**\r
 493   * @brief  Enables or disables the specified NAND Memory Bank.\r
 494   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 495   *   This parameter can be one of the following values:\r
 496   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 497   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 498   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
 499   * @retval None\r
 500   */\r
 501 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 502 {\r
 503   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 504   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 505   \r
 506   if (NewState != DISABLE)\r
 507   {\r
 508     /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
 509     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 510     {\r
 511       FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
 512     }\r
 513     else\r
 514     {\r
 515       FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
 516     }\r
 517   }\r
 518   else\r
 519   {\r
 520     /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
 521     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 522     {\r
 523       FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
 524     }\r
 525     else\r
 526     {\r
 527       FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
 528     }\r
 529   }\r
 530 }\r
 531 \r
 532 /**\r
 533   * @brief  Enables or disables the PCCARD Memory Bank.\r
 534   * @param  NewState: new state of the PCCARD Memory Bank.  \r
 535   *   This parameter can be: ENABLE or DISABLE.\r
 536   * @retval None\r
 537   */\r
 538 void FSMC_PCCARDCmd(FunctionalState NewState)\r
 539 {\r
 540   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 541   \r
 542   if (NewState != DISABLE)\r
 543   {\r
 544     /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
 545     FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
 546   }\r
 547   else\r
 548   {\r
 549     /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
 550     FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
 551   }\r
 552 }\r
 553 \r
 554 /**\r
 555   * @brief  Enables or disables the FSMC NAND ECC feature.\r
 556   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 557   *   This parameter can be one of the following values:\r
 558   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 559   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 560   * @param  NewState: new state of the FSMC NAND ECC feature.  \r
 561   *   This parameter can be: ENABLE or DISABLE.\r
 562   * @retval None\r
 563   */\r
 564 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 565 {\r
 566   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 567   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 568   \r
 569   if (NewState != DISABLE)\r
 570   {\r
 571     /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
 572     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 573     {\r
 574       FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
 575     }\r
 576     else\r
 577     {\r
 578       FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
 579     }\r
 580   }\r
 581   else\r
 582   {\r
 583     /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
 584     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 585     {\r
 586       FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
 587     }\r
 588     else\r
 589     {\r
 590       FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
 591     }\r
 592   }\r
 593 }\r
 594 \r
 595 /**\r
 596   * @brief  Returns the error correction code register value.\r
 597   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 598   *   This parameter can be one of the following values:\r
 599   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 600   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 601   * @retval The Error Correction Code (ECC) value.\r
 602   */\r
 603 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
 604 {\r
 605   uint32_t eccval = 0x00000000;\r
 606   \r
 607   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 608   {\r
 609     /* Get the ECCR2 register value */\r
 610     eccval = FSMC_Bank2->ECCR2;\r
 611   }\r
 612   else\r
 613   {\r
 614     /* Get the ECCR3 register value */\r
 615     eccval = FSMC_Bank3->ECCR3;\r
 616   }\r
 617   /* Return the error correction code value */\r
 618   return(eccval);\r
 619 }\r
 620 \r
 621 /**\r
 622   * @brief  Enables or disables the specified FSMC interrupts.\r
 623   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 624   *   This parameter can be one of the following values:\r
 625   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 626   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 627   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 628   * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
 629   *   This parameter can be any combination of the following values:\r
 630   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 631   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 632   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 633   * @param  NewState: new state of the specified FSMC interrupts.\r
 634   *   This parameter can be: ENABLE or DISABLE.\r
 635   * @retval None\r
 636   */\r
 637 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
 638 {\r
 639   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 640   assert_param(IS_FSMC_IT(FSMC_IT));    \r
 641   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 642   \r
 643   if (NewState != DISABLE)\r
 644   {\r
 645     /* Enable the selected FSMC_Bank2 interrupts */\r
 646     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 647     {\r
 648       FSMC_Bank2->SR2 |= FSMC_IT;\r
 649     }\r
 650     /* Enable the selected FSMC_Bank3 interrupts */\r
 651     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 652     {\r
 653       FSMC_Bank3->SR3 |= FSMC_IT;\r
 654     }\r
 655     /* Enable the selected FSMC_Bank4 interrupts */\r
 656     else\r
 657     {\r
 658       FSMC_Bank4->SR4 |= FSMC_IT;    \r
 659     }\r
 660   }\r
 661   else\r
 662   {\r
 663     /* Disable the selected FSMC_Bank2 interrupts */\r
 664     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 665     {\r
 666       \r
 667       FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
 668     }\r
 669     /* Disable the selected FSMC_Bank3 interrupts */\r
 670     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 671     {\r
 672       FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
 673     }\r
 674     /* Disable the selected FSMC_Bank4 interrupts */\r
 675     else\r
 676     {\r
 677       FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    \r
 678     }\r
 679   }\r
 680 }\r
 681 \r
 682 /**\r
 683   * @brief  Checks whether the specified FSMC flag is set or not.\r
 684   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 685   *   This parameter can be one of the following values:\r
 686   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 687   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 688   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 689   * @param  FSMC_FLAG: specifies the flag to check.\r
 690   *   This parameter can be one of the following values:\r
 691   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 692   *     @arg FSMC_FLAG_Level: Level detection Flag.\r
 693   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 694   *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
 695   * @retval The new state of FSMC_FLAG (SET or RESET).\r
 696   */\r
 697 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 698 {\r
 699   FlagStatus bitstatus = RESET;\r
 700   uint32_t tmpsr = 0x00000000;\r
 701   \r
 702   /* Check the parameters */\r
 703   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 704   assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
 705   \r
 706   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 707   {\r
 708     tmpsr = FSMC_Bank2->SR2;\r
 709   }  \r
 710   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 711   {\r
 712     tmpsr = FSMC_Bank3->SR3;\r
 713   }\r
 714   /* FSMC_Bank4_PCCARD*/\r
 715   else\r
 716   {\r
 717     tmpsr = FSMC_Bank4->SR4;\r
 718   } \r
 719   \r
 720   /* Get the flag status */\r
 721   if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
 722   {\r
 723     bitstatus = SET;\r
 724   }\r
 725   else\r
 726   {\r
 727     bitstatus = RESET;\r
 728   }\r
 729   /* Return the flag status */\r
 730   return bitstatus;\r
 731 }\r
 732 \r
 733 /**\r
 734   * @brief  Clears the FSMC's pending flags.\r
 735   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 736   *   This parameter can be one of the following values:\r
 737   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 738   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 739   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 740   * @param  FSMC_FLAG: specifies the flag to clear.\r
 741   *   This parameter can be any combination of the following values:\r
 742   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 743   *     @arg FSMC_FLAG_Level: Level detection Flag.\r
 744   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 745   * @retval None\r
 746   */\r
 747 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 748 {\r
 749  /* Check the parameters */\r
 750   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 751   assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
 752     \r
 753   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 754   {\r
 755     FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
 756   }  \r
 757   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 758   {\r
 759     FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
 760   }\r
 761   /* FSMC_Bank4_PCCARD*/\r
 762   else\r
 763   {\r
 764     FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
 765   }\r
 766 }\r
 767 \r
 768 /**\r
 769   * @brief  Checks whether the specified FSMC interrupt has occurred or not.\r
 770   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 771   *   This parameter can be one of the following values:\r
 772   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 773   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 774   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 775   * @param  FSMC_IT: specifies the FSMC interrupt source to check.\r
 776   *   This parameter can be one of the following values:\r
 777   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 778   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 779   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
 780   * @retval The new state of FSMC_IT (SET or RESET).\r
 781   */\r
 782 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 783 {\r
 784   ITStatus bitstatus = RESET;\r
 785   uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
 786   \r
 787   /* Check the parameters */\r
 788   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 789   assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
 790   \r
 791   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 792   {\r
 793     tmpsr = FSMC_Bank2->SR2;\r
 794   }  \r
 795   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 796   {\r
 797     tmpsr = FSMC_Bank3->SR3;\r
 798   }\r
 799   /* FSMC_Bank4_PCCARD*/\r
 800   else\r
 801   {\r
 802     tmpsr = FSMC_Bank4->SR4;\r
 803   } \r
 804   \r
 805   itstatus = tmpsr & FSMC_IT;\r
 806   \r
 807   itenable = tmpsr & (FSMC_IT >> 3);\r
 808   if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))\r
 809   {\r
 810     bitstatus = SET;\r
 811   }\r
 812   else\r
 813   {\r
 814     bitstatus = RESET;\r
 815   }\r
 816   return bitstatus; \r
 817 }\r
 818 \r
 819 /**\r
 820   * @brief  Clears the FSMC's interrupt pending bits.\r
 821   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 822   *   This parameter can be one of the following values:\r
 823   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 824   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 825   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 826   * @param  FSMC_IT: specifies the interrupt pending bit to clear.\r
 827   *   This parameter can be any combination of the following values:\r
 828   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 829   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 830   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 831   * @retval None\r
 832   */\r
 833 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 834 {\r
 835   /* Check the parameters */\r
 836   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 837   assert_param(IS_FSMC_IT(FSMC_IT));\r
 838     \r
 839   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 840   {\r
 841     FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
 842   }  \r
 843   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 844   {\r
 845     FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
 846   }\r
 847   /* FSMC_Bank4_PCCARD*/\r
 848   else\r
 849   {\r
 850     FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
 851   }\r
 852 }\r
 853 \r
 854 /**\r
 855   * @}\r
 856   */ \r
 857 \r
 858 /**\r
 859   * @}\r
 860   */\r
 861 \r
 862 /**\r
 863   * @}\r
 864   */\r
 865 \r
 866 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/\r