jspc29.x-matter.uni-frankfurt.de Git - mvd_firmware.git/blob

   1 ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************\r
   2 ;* File Name          : startup_stm32f10x_hd_vl.s\r
   3 ;* Author             : MCD Application Team\r
   4 ;* Version            : V3.5.0\r
   5 ;* Date               : 11-March-2011\r
   6 ;* Description        : STM32F10x High Density Value Line Devices vector table  \r
   7 ;*                      for MDK-ARM toolchain.  \r
   8 ;*                      This module performs:\r
   9 ;*                      - Set the initial SP\r
  10 ;*                      - Set the initial PC == Reset_Handler\r
  11 ;*                      - Set the vector table entries with the exceptions ISR address\r
  12 ;*                      - Configure the clock system and also configure the external \r
  13 ;*                        SRAM mounted on STM32100E-EVAL board to be used as data \r
  14 ;*                        memory (optional, to be enabled by user)\r
  15 ;*                      - Branches to __main in the C library (which eventually\r
  16 ;*                        calls main()).\r
  17 ;*                      After Reset the CortexM3 processor is in Thread mode,\r
  18 ;*                      priority is Privileged, and the Stack is set to Main.\r
  19 ;* <<< Use Configuration Wizard in Context Menu >>>   \r
  20 ;*******************************************************************************\r
  21 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  22 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
  23 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
  24 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
  25 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
  26 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  27 ;*******************************************************************************\r
  28 \r
  29 ; Amount of memory (in bytes) allocated for Stack\r
  30 ; Tailor this value to your application needs\r
  31 ; <h> Stack Configuration\r
  32 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  33 ; </h>\r
  34 \r
  35 Stack_Size      EQU     0x00000400\r
  36 \r
  37                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  38 Stack_Mem       SPACE   Stack_Size\r
  39 __initial_sp\r
  40 \r
  41 \r
  42 ; <h> Heap Configuration\r
  43 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  44 ; </h>\r
  45 \r
  46 Heap_Size       EQU     0x00000200\r
  47 \r
  48                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  49 __heap_base\r
  50 Heap_Mem        SPACE   Heap_Size\r
  51 __heap_limit\r
  52 \r
  53                 PRESERVE8\r
  54                 THUMB\r
  55 \r
  56 \r
  57 ; Vector Table Mapped to Address 0 at Reset\r
  58                 AREA    RESET, DATA, READONLY\r
  59                 EXPORT  __Vectors\r
  60                 EXPORT  __Vectors_End\r
  61                 EXPORT  __Vectors_Size\r
  62 \r
  63 __Vectors       DCD     __initial_sp                    ; Top of Stack\r
  64                 DCD     Reset_Handler                   ; Reset Handler\r
  65                 DCD     NMI_Handler                     ; NMI Handler\r
  66                 DCD     HardFault_Handler               ; Hard Fault Handler\r
  67                 DCD     MemManage_Handler               ; MPU Fault Handler\r
  68                 DCD     BusFault_Handler                ; Bus Fault Handler\r
  69                 DCD     UsageFault_Handler              ; Usage Fault Handler\r
  70                 DCD     0                               ; Reserved\r
  71                 DCD     0                               ; Reserved\r
  72                 DCD     0                               ; Reserved\r
  73                 DCD     0                               ; Reserved\r
  74                 DCD     SVC_Handler                     ; SVCall Handler\r
  75                 DCD     DebugMon_Handler                ; Debug Monitor Handler\r
  76                 DCD     0                               ; Reserved\r
  77                 DCD     PendSV_Handler                  ; PendSV Handler\r
  78                 DCD     SysTick_Handler                 ; SysTick Handler\r
  79 \r
  80                 ; External Interrupts\r
  81                 DCD     WWDG_IRQHandler                 ; Window Watchdog\r
  82                 DCD     PVD_IRQHandler                  ; PVD through EXTI Line detect\r
  83                 DCD     TAMPER_IRQHandler               ; Tamper\r
  84                 DCD     RTC_IRQHandler                  ; RTC\r
  85                 DCD     FLASH_IRQHandler                ; Flash\r
  86                 DCD     RCC_IRQHandler                  ; RCC\r
  87                 DCD     EXTI0_IRQHandler                ; EXTI Line 0\r
  88                 DCD     EXTI1_IRQHandler                ; EXTI Line 1\r
  89                 DCD     EXTI2_IRQHandler                ; EXTI Line 2\r
  90                 DCD     EXTI3_IRQHandler                ; EXTI Line 3\r
  91                 DCD     EXTI4_IRQHandler                ; EXTI Line 4\r
  92                 DCD     DMA1_Channel1_IRQHandler        ; DMA1 Channel 1\r
  93                 DCD     DMA1_Channel2_IRQHandler        ; DMA1 Channel 2\r
  94                 DCD     DMA1_Channel3_IRQHandler        ; DMA1 Channel 3\r
  95                 DCD     DMA1_Channel4_IRQHandler        ; DMA1 Channel 4\r
  96                 DCD     DMA1_Channel5_IRQHandler        ; DMA1 Channel 5\r
  97                 DCD     DMA1_Channel6_IRQHandler        ; DMA1 Channel 6\r
  98                 DCD     DMA1_Channel7_IRQHandler        ; DMA1 Channel 7\r
  99                 DCD     ADC1_IRQHandler                 ; ADC1\r
 100                 DCD     0                               ; Reserved\r
 101                 DCD     0                               ; Reserved\r
 102                 DCD     0                               ; Reserved\r
 103                 DCD     0                               ; Reserved\r
 104                 DCD     EXTI9_5_IRQHandler              ; EXTI Line 9..5\r
 105                 DCD     TIM1_BRK_TIM15_IRQHandler       ; TIM1 Break and TIM15\r
 106                 DCD     TIM1_UP_TIM16_IRQHandler        ; TIM1 Update and TIM16\r
 107                 DCD     TIM1_TRG_COM_TIM17_IRQHandler   ; TIM1 Trigger and Commutation and TIM17\r
 108                 DCD     TIM1_CC_IRQHandler              ; TIM1 Capture Compare\r
 109                 DCD     TIM2_IRQHandler                 ; TIM2\r
 110                 DCD     TIM3_IRQHandler                 ; TIM3\r
 111                 DCD     TIM4_IRQHandler                 ; TIM4\r
 112                 DCD     I2C1_EV_IRQHandler              ; I2C1 Event\r
 113                 DCD     I2C1_ER_IRQHandler              ; I2C1 Error\r
 114                 DCD     I2C2_EV_IRQHandler              ; I2C2 Event\r
 115                 DCD     I2C2_ER_IRQHandler              ; I2C2 Error\r
 116                 DCD     SPI1_IRQHandler                 ; SPI1\r
 117                 DCD     SPI2_IRQHandler                 ; SPI2\r
 118                 DCD     USART1_IRQHandler               ; USART1\r
 119                 DCD     USART2_IRQHandler               ; USART2\r
 120                 DCD     USART3_IRQHandler               ; USART3\r
 121                 DCD     EXTI15_10_IRQHandler            ; EXTI Line 15..10\r
 122                 DCD     RTCAlarm_IRQHandler             ; RTC Alarm through EXTI Line\r
 123                 DCD     CEC_IRQHandler                  ; HDMI-CEC\r
 124                 DCD     TIM12_IRQHandler                ; TIM12\r
 125                 DCD     TIM13_IRQHandler                ; TIM13 \r
 126                 DCD     TIM14_IRQHandler                ; TIM14\r
 127                 DCD     0                               ; Reserved\r
 128                 DCD     0                               ; Reserved\r
 129                 DCD     0                               ; Reserved\r
 130                 DCD     0                               ; Reserved\r
 131                 DCD     TIM5_IRQHandler                 ; TIM5\r
 132                 DCD     SPI3_IRQHandler                 ; SPI3\r
 133                 DCD     UART4_IRQHandler                ; UART4\r
 134                 DCD     UART5_IRQHandler                ; UART5\r
 135                 DCD     TIM6_DAC_IRQHandler             ; TIM6 and DAC underrun\r
 136                 DCD     TIM7_IRQHandler                 ; TIM7\r
 137                 DCD     DMA2_Channel1_IRQHandler        ; DMA2 Channel1\r
 138                 DCD     DMA2_Channel2_IRQHandler        ; DMA2 Channel2\r
 139                 DCD     DMA2_Channel3_IRQHandler        ; DMA2 Channel3\r
 140                 DCD     DMA2_Channel4_5_IRQHandler      ; DMA2 Channel4 & Channel5\r
 141                 DCD     DMA2_Channel5_IRQHandler        ; DMA2 Channel5                \r
 142 __Vectors_End\r
 143 \r
 144 __Vectors_Size  EQU  __Vectors_End - __Vectors\r
 145 \r
 146                 AREA    |.text|, CODE, READONLY\r
 147 \r
 148 ; Reset handler\r
 149 Reset_Handler    PROC\r
 150                  EXPORT  Reset_Handler             [WEAK]\r
 151      IMPORT  __main\r
 152      IMPORT  SystemInit\r
 153                  LDR     R0, =SystemInit\r
 154                  BLX     R0\r
 155                  LDR     R0, =__main\r
 156                  BX      R0\r
 157                  ENDP\r
 158 \r
 159 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 160 \r
 161 NMI_Handler     PROC\r
 162                 EXPORT  NMI_Handler                      [WEAK]\r
 163                 B       .\r
 164                 ENDP\r
 165 HardFault_Handler\\r
 166                 PROC\r
 167                 EXPORT  HardFault_Handler                [WEAK]\r
 168                 B       .\r
 169                 ENDP\r
 170 MemManage_Handler\\r
 171                 PROC\r
 172                 EXPORT  MemManage_Handler                [WEAK]\r
 173                 B       .\r
 174                 ENDP\r
 175 BusFault_Handler\\r
 176                 PROC\r
 177                 EXPORT  BusFault_Handler                 [WEAK]\r
 178                 B       .\r
 179                 ENDP\r
 180 UsageFault_Handler\\r
 181                 PROC\r
 182                 EXPORT  UsageFault_Handler               [WEAK]\r
 183                 B       .\r
 184                 ENDP\r
 185 SVC_Handler     PROC\r
 186                 EXPORT  SVC_Handler                      [WEAK]\r
 187                 B       .\r
 188                 ENDP\r
 189 DebugMon_Handler\\r
 190                 PROC\r
 191                 EXPORT  DebugMon_Handler                 [WEAK]\r
 192                 B       .\r
 193                 ENDP\r
 194 PendSV_Handler  PROC\r
 195                 EXPORT  PendSV_Handler                   [WEAK]\r
 196                 B       .\r
 197                 ENDP\r
 198 SysTick_Handler PROC\r
 199                 EXPORT  SysTick_Handler                  [WEAK]\r
 200                 B       .\r
 201                 ENDP\r
 202 \r
 203 Default_Handler PROC\r
 204 \r
 205                 EXPORT  WWDG_IRQHandler                  [WEAK]\r
 206                 EXPORT  PVD_IRQHandler                   [WEAK]\r
 207                 EXPORT  TAMPER_IRQHandler                [WEAK]\r
 208                 EXPORT  RTC_IRQHandler                   [WEAK]\r
 209                 EXPORT  FLASH_IRQHandler                 [WEAK]\r
 210                 EXPORT  RCC_IRQHandler                   [WEAK]\r
 211                 EXPORT  EXTI0_IRQHandler                 [WEAK]\r
 212                 EXPORT  EXTI1_IRQHandler                 [WEAK]\r
 213                 EXPORT  EXTI2_IRQHandler                 [WEAK]\r
 214                 EXPORT  EXTI3_IRQHandler                 [WEAK]\r
 215                 EXPORT  EXTI4_IRQHandler                 [WEAK]\r
 216                 EXPORT  DMA1_Channel1_IRQHandler         [WEAK]\r
 217                 EXPORT  DMA1_Channel2_IRQHandler         [WEAK]\r
 218                 EXPORT  DMA1_Channel3_IRQHandler         [WEAK]\r
 219                 EXPORT  DMA1_Channel4_IRQHandler         [WEAK]\r
 220                 EXPORT  DMA1_Channel5_IRQHandler         [WEAK]\r
 221                 EXPORT  DMA1_Channel6_IRQHandler         [WEAK]\r
 222                 EXPORT  DMA1_Channel7_IRQHandler         [WEAK]\r
 223                 EXPORT  ADC1_IRQHandler                  [WEAK]\r
 224                 EXPORT  EXTI9_5_IRQHandler               [WEAK]\r
 225                 EXPORT  TIM1_BRK_TIM15_IRQHandler        [WEAK]\r
 226                 EXPORT  TIM1_UP_TIM16_IRQHandler         [WEAK]\r
 227                 EXPORT  TIM1_TRG_COM_TIM17_IRQHandler    [WEAK]\r
 228                 EXPORT  TIM1_CC_IRQHandler               [WEAK]\r
 229                 EXPORT  TIM2_IRQHandler                  [WEAK]\r
 230                 EXPORT  TIM3_IRQHandler                  [WEAK]\r
 231                 EXPORT  TIM4_IRQHandler                  [WEAK]\r
 232                 EXPORT  I2C1_EV_IRQHandler               [WEAK]\r
 233                 EXPORT  I2C1_ER_IRQHandler               [WEAK]\r
 234                 EXPORT  I2C2_EV_IRQHandler               [WEAK]\r
 235                 EXPORT  I2C2_ER_IRQHandler               [WEAK]\r
 236                 EXPORT  SPI1_IRQHandler                  [WEAK]\r
 237                 EXPORT  SPI2_IRQHandler                  [WEAK]\r
 238                 EXPORT  USART1_IRQHandler                [WEAK]\r
 239                 EXPORT  USART2_IRQHandler                [WEAK]\r
 240                 EXPORT  USART3_IRQHandler                [WEAK]\r
 241                 EXPORT  EXTI15_10_IRQHandler             [WEAK]\r
 242                 EXPORT  RTCAlarm_IRQHandler              [WEAK]\r
 243                 EXPORT  CEC_IRQHandler                   [WEAK]\r
 244                 EXPORT  TIM12_IRQHandler                 [WEAK]\r
 245                 EXPORT  TIM13_IRQHandler                 [WEAK]\r
 246                 EXPORT  TIM14_IRQHandler                 [WEAK]\r
 247                 EXPORT  TIM5_IRQHandler                  [WEAK]\r
 248                 EXPORT  SPI3_IRQHandler                  [WEAK]\r
 249                 EXPORT  UART4_IRQHandler                 [WEAK]\r
 250                 EXPORT  UART5_IRQHandler                 [WEAK]                \r
 251                 EXPORT  TIM6_DAC_IRQHandler              [WEAK]\r
 252                 EXPORT  TIM7_IRQHandler                  [WEAK]\r
 253                 EXPORT  DMA2_Channel1_IRQHandler         [WEAK]\r
 254                 EXPORT  DMA2_Channel2_IRQHandler         [WEAK]\r
 255                 EXPORT  DMA2_Channel3_IRQHandler         [WEAK]\r
 256                 EXPORT  DMA2_Channel4_5_IRQHandler       [WEAK]\r
 257                 EXPORT  DMA2_Channel5_IRQHandler         [WEAK]                \r
 258 \r
 259 WWDG_IRQHandler\r
 260 PVD_IRQHandler\r
 261 TAMPER_IRQHandler\r
 262 RTC_IRQHandler\r
 263 FLASH_IRQHandler\r
 264 RCC_IRQHandler\r
 265 EXTI0_IRQHandler\r
 266 EXTI1_IRQHandler\r
 267 EXTI2_IRQHandler\r
 268 EXTI3_IRQHandler\r
 269 EXTI4_IRQHandler\r
 270 DMA1_Channel1_IRQHandler\r
 271 DMA1_Channel2_IRQHandler\r
 272 DMA1_Channel3_IRQHandler\r
 273 DMA1_Channel4_IRQHandler\r
 274 DMA1_Channel5_IRQHandler\r
 275 DMA1_Channel6_IRQHandler\r
 276 DMA1_Channel7_IRQHandler\r
 277 ADC1_IRQHandler\r
 278 EXTI9_5_IRQHandler\r
 279 TIM1_BRK_TIM15_IRQHandler\r
 280 TIM1_UP_TIM16_IRQHandler\r
 281 TIM1_TRG_COM_TIM17_IRQHandler\r
 282 TIM1_CC_IRQHandler\r
 283 TIM2_IRQHandler\r
 284 TIM3_IRQHandler\r
 285 TIM4_IRQHandler\r
 286 I2C1_EV_IRQHandler\r
 287 I2C1_ER_IRQHandler\r
 288 I2C2_EV_IRQHandler\r
 289 I2C2_ER_IRQHandler\r
 290 SPI1_IRQHandler\r
 291 SPI2_IRQHandler\r
 292 USART1_IRQHandler\r
 293 USART2_IRQHandler\r
 294 USART3_IRQHandler\r
 295 EXTI15_10_IRQHandler\r
 296 RTCAlarm_IRQHandler\r
 297 CEC_IRQHandler\r
 298 TIM12_IRQHandler\r
 299 TIM13_IRQHandler\r
 300 TIM14_IRQHandler\r
 301 TIM5_IRQHandler\r
 302 SPI3_IRQHandler\r
 303 UART4_IRQHandler\r
 304 UART5_IRQHandler\r
 305 TIM6_DAC_IRQHandler\r
 306 TIM7_IRQHandler\r
 307 DMA2_Channel1_IRQHandler\r
 308 DMA2_Channel2_IRQHandler\r
 309 DMA2_Channel3_IRQHandler\r
 310 DMA2_Channel4_5_IRQHandler\r
 311 DMA2_Channel5_IRQHandler\r
 312                 B       .\r
 313 \r
 314                 ENDP\r
 315 \r
 316                 ALIGN\r
 317 \r
 318 ;*******************************************************************************\r
 319 ; User Stack and Heap initialization\r
 320 ;*******************************************************************************\r
 321                  IF      :DEF:__MICROLIB           \r
 322                 \r
 323                  EXPORT  __initial_sp\r
 324                  EXPORT  __heap_base\r
 325                  EXPORT  __heap_limit\r
 326                 \r
 327                  ELSE\r
 328                 \r
 329                  IMPORT  __use_two_region_memory\r
 330                  EXPORT  __user_initial_stackheap\r
 331                  \r
 332 __user_initial_stackheap\r
 333 \r
 334                  LDR     R0, =  Heap_Mem\r
 335                  LDR     R1, =(Stack_Mem + Stack_Size)\r
 336                  LDR     R2, = (Heap_Mem +  Heap_Size)\r
 337                  LDR     R3, = Stack_Mem\r
 338                  BX      LR\r
 339 \r
 340                  ALIGN\r
 341 \r
 342                  ENDIF\r
 343 \r
 344                  END\r
 345 \r
 346 ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****\r