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(parent: 92f82c6) | patch
trb_parser: Add missing sensitivity-list signals
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Fri, 11 Sep 2020 14:17:12 +0000 (16:17 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Fri, 11 Sep 2020 14:17:12 +0000 (16:17 +0200)
commit0e57dc604391db8f70d2f3b6f935269126f0513e
tree7807f3c82329bed5dbf56088449e32222d488993tree | snapshot
parent92f82c661957c7ef43653329398ed2a819face70commit | diff
trb_parser: Add missing sensitivity-list signals
hub_test/src/trb_parser.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware