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(parent: e247d04) | patch
Add coincidence logic to trigger generation;
authorJan Michel <j.michel@gsi.de>
Fri, 3 Feb 2017 17:42:49 +0000 (18:42 +0100)
committerJan Michel <j.michel@gsi.de>
Fri, 3 Feb 2017 17:42:49 +0000 (18:42 +0100)
commit0e6bd41b57e2f0c40b4c561f022fbcf513d6ea38
treea315d1c243e916cadf3f885b60fe0a20c3956646tree | snapshot
parente247d045bafaa1d6a4b87c851a00f297275061b0commit | diff
Add coincidence logic to trigger generation;
TRB3 blank project update
base/code/input_statistics.vhd diff | blob | history
base/code/input_to_trigger_logic_record.vhd diff | blob | history
blank/config_compile_frankfurt.pl diff | blob | history
blank/trb3_periph_blank.vhd diff | blob | history
TRB3 VHDL