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(parent: 8371260) | patch
TDC source files are added - Cahit
authorhadaq <hadaq>
Fri, 28 Oct 2011 14:59:44 +0000 (14:59 +0000)
committerhadaq <hadaq>
Fri, 28 Oct 2011 14:59:44 +0000 (14:59 +0000)
commit0e8909d50b19c9956d787c4f508eaedd7e147954
tree91b8633f55c9ed6356eff33f3b4de574bd5f56c3tree | snapshot
parent8371260f36812127af67ce91673f5bf77ff112b2commit | diff
TDC source files are added - Cahit
14 files changed:
base/cores/bit_sync.vhd [new file with mode: 0644] blob
base/cores/edge_to_pulse_fast.vhd [new file with mode: 0644] blob
base/cores/f_divider.vhd [new file with mode: 0644] blob
base/cores/signal_sync.vhd [new file with mode: 0644] blob
base/cores/up_counter.vhd [new file with mode: 0644] blob
base/tdc_source_files/Adder_288.vhd [new file with mode: 0644] blob
base/tdc_source_files/Adder_320.vhd [new file with mode: 0644] blob
base/tdc_source_files/Channel_288.vhd [new file with mode: 0644] blob
base/tdc_source_files/Channel_320.vhd [new file with mode: 0644] blob
base/tdc_source_files/Encoder_288_Bit.vhd [new file with mode: 0644] blob
base/tdc_source_files/Encoder_320_Bit.vhd [new file with mode: 0644] blob
base/tdc_source_files/FIFO_32x512_Oreg.vhd [new file with mode: 0644] blob
base/tdc_source_files/ROM_FIFO.vhd [new file with mode: 0644] blob
base/tdc_source_files/TDC.vhd [new file with mode: 0644] blob
TRB3 VHDL