]> jspc29.x-matter.uni-frankfurt.de Git - ctsaddon.git/commit
*** empty log message ***
authorhadaq <hadaq>
Tue, 3 Jan 2012 12:38:47 +0000 (12:38 +0000)
committerhadaq <hadaq>
Tue, 3 Jan 2012 12:38:47 +0000 (12:38 +0000)
commit0f4b6224a64346343f8e2d2836f551c0838efbcb
treec2f52767b4270e88bdb44fd48cea2a5517069329
parent67374e13b19f1890f7b02dd0f9689d3e8ed269b0
*** empty log message ***
94 files changed:
beam_structure_fifo.lpc [new file with mode: 0644]
beam_structure_fifo.vhd [new file with mode: 0644]
cts_align_signals.vhd [new file with mode: 0644]
cts_beam_structure.vhd [new file with mode: 0644]
cts_cal_screset_gen.vhd [new file with mode: 0644]
cts_components.vhd [new file with mode: 0644]
cts_delay.vhd [new file with mode: 0644]
cts_delay_large.vhd [new file with mode: 0644]
cts_downscale.vhd [new file with mode: 0644]
cts_eb_ip_switch.vhd [new file with mode: 0644]
cts_fpga1.lpf [new file with mode: 0644]
cts_fpga1.prj
cts_fpga1.vhd
cts_fpga1_compile.pl [new file with mode: 0755]
cts_fpga1_tb.vhd [new file with mode: 0644]
cts_fpga1_test.prj [new file with mode: 0644]
cts_fpga1_test.vhd [new file with mode: 0644]
cts_fpga1_test_compile.pl [new file with mode: 0755]
cts_fpga1_test_trb_fpga_on.xcf [new file with mode: 0644]
cts_fpga1_to_fpga2.vhd [new file with mode: 0644]
cts_fpga1_trb_fpga_on.xcf [new file with mode: 0644]
cts_fpga1_trb_no_fpga.xcf [new file with mode: 0644]
cts_fpga2.lpf [new file with mode: 0644]
cts_fpga2_compile.pl [new file with mode: 0755]
cts_fpga2_lvl1_data_downscale.vhd [new file with mode: 0644]
cts_fpga2_lvl1_lvl2_fifo.vhd [new file with mode: 0644]
cts_fpga2_lvl2.vhd [new file with mode: 0644]
cts_fpga2_reg_interface.vhd [new file with mode: 0644]
cts_fpga2_reg_mem.lpc [new file with mode: 0644]
cts_fpga2_reg_mem.vhd [new file with mode: 0644]
cts_fpga2_to_fpga1.vhd [new file with mode: 0644]
cts_fpga2_trb_fpga_on.xcf [new file with mode: 0644]
cts_fpga2_trb_no_fpga.xcf [new file with mode: 0644]
cts_fpga2_trig_gen.vhd [new file with mode: 0644]
cts_one_clock.vhd [new file with mode: 0644]
cts_polarity_check.vhd [new file with mode: 0644]
cts_readout.vhd [new file with mode: 0644]
cts_readout_data_buff.lpc [new file with mode: 0644]
cts_readout_data_buff.vhd [new file with mode: 0644]
cts_set_width.vhd [new file with mode: 0644]
cts_set_width_large.vhd [new file with mode: 0644]
cts_simple_data_transport.vhd [new file with mode: 0644]
cts_simulation_tb.mpf [new file with mode: 0644]
cts_trigger_logic.vhd [new file with mode: 0755]
cts_width_rom.lpc [new file with mode: 0644]
cts_width_rom.mem [new file with mode: 0644]
cts_width_rom.vhd [new file with mode: 0644]
ddr2_12out_clkdiv.vhd [new file with mode: 0644]
ddr2_16inputs.vhd [new file with mode: 0644]
ddr2_3out_clkdiv.vhd [new file with mode: 0644]
ddr2_busses.vhd [new file with mode: 0644]
ddr_lvl1_trigger.vhd [new file with mode: 0644]
delay_fifo.vhd [new file with mode: 0644]
dll_edge.vhd [new file with mode: 0644]
dll_in400_out200.vhd [new file with mode: 0644]
ecp2m_lvl2_trigger_buffer_fifo_1kW.lpc [new file with mode: 0644]
ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd [new file with mode: 0644]
edge_clk.lpc [new file with mode: 0644]
etrax_reg_mem.vhd [new file with mode: 0644]
fifo16bit_synch.vhd [new file with mode: 0644]
fifo_16bit_to_32bit.lpc [new file with mode: 0644]
fifo_16bit_to_32bit.vhd [new file with mode: 0644]
fifo_1bit_to_32bit.lpc [new file with mode: 0644]
fifo_1bit_to_32bit.vhd [new file with mode: 0644]
fifo_2bit_to_32bit.lpc [new file with mode: 0644]
fifo_2bit_to_32bit.vhd [new file with mode: 0644]
fifo_4bit_to_32bit.lpc [new file with mode: 0644]
fifo_4bit_to_32bit.vhd [new file with mode: 0644]
fifo_8bit_to_32bit.lpc [new file with mode: 0644]
fifo_8bit_to_32bit.vhd [new file with mode: 0644]
multiplicity.vhd [new file with mode: 0644]
pll_in200_out40.lpc [new file with mode: 0644]
pll_in200_out40.vhd [new file with mode: 0644]
pll_in200_out400.vhd [new file with mode: 0644]
ram_register.lpc [new file with mode: 0644]
ram_register.vhd [new file with mode: 0644]
ram_start_values.mem [new file with mode: 0644]
regmem.mem [new file with mode: 0644]
scm_fifo_16bit_to_32bit.lpc [new file with mode: 0644]
scm_fifo_16bit_to_32bit.vhd [new file with mode: 0644]
scm_fifo_1bit_to_32bit.lpc [new file with mode: 0644]
scm_fifo_1bit_to_32bit.vhd [new file with mode: 0644]
scm_fifo_2bit_to_32bit.lpc [new file with mode: 0644]
scm_fifo_2bit_to_32bit.vhd [new file with mode: 0644]
scm_fifo_4bit_to_32bit.lpc [new file with mode: 0644]
scm_fifo_4bit_to_32bit.vhd [new file with mode: 0644]
scm_fifo_8bit_to_32bit.lpc [new file with mode: 0644]
scm_fifo_8bit_to_32bit.vhd [new file with mode: 0644]
serdes_gbe_0.txt [new file with mode: 0644]
serdes_gbe_0_200.txt [new file with mode: 0755]
simulation.pl [new file with mode: 0755]
version.vhd [new file with mode: 0644]
widthGenerator.pl [new file with mode: 0755]
widthGenerator2.pl [new file with mode: 0755]