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(parent: 884ce30) | patch
added correct PLL for 200MHz and 150MHz calibration oscillator, mt
authorHADES DAQ <M.Traxler@gsi.de>
Fri, 21 Oct 2022 14:32:50 +0000 (16:32 +0200)
committerHADES DAQ <M.Traxler@gsi.de>
Fri, 21 Oct 2022 14:32:50 +0000 (16:32 +0200)
commit1c61e5b30dceb38c5aa7a526951ac7637093667c
treecc723b59e111a80248e7f2c6be02449f54f5f74etree | snapshot
parent884ce30eb2d524b483ff3c622f84af47acb653b2commit | diff
added correct PLL for 200MHz and 150MHz calibration oscillator, mt
base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.cst [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.fdc [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.lpc [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in150_out50/pll_in150_out50.vhd [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.cst [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.fdc [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.lpc [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd [new file with mode: 0644] blob
The FPGA-TDC files