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(parent: 30cc0b4) | patch
adding testbench for input_to_trigger_logic
authorJan Michel <j.michel@gsi.de>
Mon, 21 Mar 2016 14:50:29 +0000 (15:50 +0100)
committerJan Michel <j.michel@gsi.de>
Mon, 21 Mar 2016 14:50:29 +0000 (15:50 +0100)
commit232ad5d7dcf33f21339511d2a8dad3e377aa55e6
tree2b6435b5cb96f89f55abcb1e5c6ee2b5f4b40112tree | snapshot
parent30cc0b4aa93514b7bc91f7f30885994074121086commit | diff
adding testbench for input_to_trigger_logic
testbenches/tb_input_to_trigger_logic_record.vhd [new file with mode: 0644] blob
TrbNet VHDL code