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(parent: cdeb5a1) | patch
added fifo and pll IPs for ecp5
authorCahit <c.ugur@gsi.de>
Wed, 23 Mar 2016 13:55:49 +0000 (14:55 +0100)
committerCahit <c.ugur@gsi.de>
Wed, 23 Mar 2016 13:55:49 +0000 (14:55 +0100)
commit247e0ab86cbbdadea213a3503b632bb2f73a25e4
treee64ea14cfa9f8d0d499f7f73451c62d94a020f62tree | snapshot
parentcdeb5a14f4b440cbe4dd548fd9496f53216fb131commit | diff
added fifo and pll IPs for ecp5
13 files changed:
.gitignore [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.sbx [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.sbx [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.sbx [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.sbx [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.sbx [new file with mode: 0644] blob
base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.sbx [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd [new file with mode: 0644] blob
The FPGA-TDC files