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(parent: bbb6328) | patch
Fix placement of logic in regions. Fix detection of length of reference time signal.
authorJan Michel <j.michel@gsi.de>
Fri, 2 Feb 2018 10:48:38 +0000 (11:48 +0100)
committerJan Michel <j.michel@gsi.de>
Fri, 2 Feb 2018 10:48:38 +0000 (11:48 +0100)
commit2a2a67ac4a7c3bc5c33e902b094bfdbc79bc9e50
tree38586766abc710beabeeef9988400fc2304bafd5tree | snapshot
parentbbb63283d00a0601fee0dfaa12a3c3014a103486commit | diff
Fix placement of logic in regions. Fix detection of length of reference time signal.
releases/tdc_v2.3/Channel_200.vhd diff | blob | history
releases/tdc_v2.3/TriggerHandler.vhd diff | blob | history
releases/tdc_v2.3/trb3_periph_ADA.vhd diff | blob | history
The FPGA-TDC files