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(parent: 4fd30ad) | patch
without double synchroniser
authorhadaq <hadaq>
Mon, 27 Aug 2012 12:44:33 +0000 (12:44 +0000)
committerhadaq <hadaq>
Mon, 27 Aug 2012 12:44:33 +0000 (12:44 +0000)
commit2bc864e1ff806ac47a56ecaa4c4de763a946dbb9
tree04016453781a8fd50eab5ad9bec72848c2d445cftree | snapshot
parent4fd30ad5a90c6e098d02e15fd9dcbb34cd0cca75commit | diff
without double synchroniser
12 files changed:
tdc_releases/tdc_v0.5/Adder_304.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/Channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/ROM_FIFO.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/ROM_encoder_3.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/Reference_channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/TDC.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/bit_sync.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/trb3_periph.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/trb3_periph_constraints.lpf [new file with mode: 0644] blob
tdc_releases/tdc_v0.5/up_counter.vhd [new file with mode: 0644] blob
TRB3 VHDL