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(parent: 0e70fe0) | patch
Update ECP5 serdes files
authorJan Michel <j.michel@gsi.de>
Thu, 25 Apr 2019 12:06:33 +0000 (14:06 +0200)
committerJan Michel <j.michel@gsi.de>
Thu, 25 Apr 2019 12:06:33 +0000 (14:06 +0200)
commit300bb7e95984aaa52aa446e78665c38a77da12b1
treefc8f9ce6e344bac98a07778cb7fdd6b62de48d52tree | snapshot
parent0e70fe0eef12578241f98d41858b5d1597074cc8commit | diff
Update ECP5 serdes files
media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.lpc diff | blob | history
media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx diff | blob | history
media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd diff | blob | history
media_interfaces/ecp5/serdes_sync_0/serdes_sync_0_softlogic.v diff | blob | history
TrbNet VHDL code