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(parent: cccdaa7) | patch
delayes BUS HANDLER read signal one clock cycle to match the MULTICYCLE constraint
authorCahit <c.ugur@gsi.de>
Tue, 26 Jan 2016 08:26:46 +0000 (09:26 +0100)
committerCahit <c.ugur@gsi.de>
Tue, 26 Jan 2016 08:26:46 +0000 (09:26 +0100)
commit36f7c5ebe78a152c74042aca31ae78d1738214e6
treee888e96b1d4e152a01538923dc5d2ffc8e905113tree | snapshot
parentcccdaa70d2e1c605fd6731b92e14635a08496a9fcommit | diff
delayes BUS HANDLER read signal one clock cycle to match the MULTICYCLE constraint
releases/tdc_v2.3/BusHandler_record.vhd diff | blob | history
The FPGA-TDC files