]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commit
jspc29 / trbnet.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0abbf35) | patch
First try, will most likely not compile.
authorhadaq <hadaq>
Wed, 30 Jun 2010 15:50:00 +0000 (15:50 +0000)
committerhadaq <hadaq>
Wed, 30 Jun 2010 15:50:00 +0000 (15:50 +0000)
commit3b48a371b85649d5fea3383be87db4faad153fdb
treeccc30eaa64153c5f8d3140cd62eac844e7974df3tree | snapshot
parent0abbf35fe71bc61d804927850a8a4ad511fd761acommit | diff
First try, will most likely not compile.
Clock domains must be checked completely.
Reset sequence most likely not suitable.
RX delay registers between SerDes and byte swapper removed.
Too many bullshit comments in.
media_interfaces/trb_net16_med_scm_sfp_gbe.vhd [new file with mode: 0755] blob
TrbNet VHDL code