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(parent: e4f3939) | patch
add new ECP5 fifos
authorJan Michel <j.michel@gsi.de>
Mon, 9 Aug 2021 12:01:24 +0000 (14:01 +0200)
committerJan Michel <j.michel@gsi.de>
Mon, 9 Aug 2021 12:01:24 +0000 (14:01 +0200)
commit43d40d26391b76dd534dd8896eb38f6957d0a69f
tree7dbe8bd9dcfcd24ed37492bcd90eca8bd15fd45ftree | snapshot
parente4f39393a07f1d348d384795fe9ac11d72914b40commit | diff
add new ECP5 fifos
lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.lpc [new file with mode: 0644] blob
lattice/ecp5/FIFO/fifo_36x32/fifo_36x32.vhd [new file with mode: 0644] blob
lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.lpc [new file with mode: 0644] blob
lattice/ecp5/FIFO/fifo_36x32_oreg/fifo_36x32_oreg.vhd [new file with mode: 0644] blob
lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.lpc [new file with mode: 0644] blob
lattice/ecp5/FIFO/fifo_36x512_dualport_oreg/fifo_36x512_dualport_oreg.vhd [new file with mode: 0644] blob
lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.lpc diff | blob | history
lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd diff | blob | history
TrbNet VHDL code