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(parent: 2596cc3) | patch
hub_test: Add MBS trigger output ports
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Fri, 4 Sep 2020 14:21:07 +0000 (16:21 +0200)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Fri, 4 Sep 2020 14:21:07 +0000 (16:21 +0200)
commit4ce36c7afcc1b4a3b2e4eaede22d78a21ead8a07
treec4b63910c9b5e211bb3047ff2968c609a3adce86tree | snapshot
parent2596cc3576e3ae82a336cc40921f7a7d452038afcommit | diff
hub_test: Add MBS trigger output ports

Add a test trigger signal that corresponds to the microslice timing.
Output the signal to the CRI's four coaxial (U.FL) LVDS connectors. This
can be used for investigations with a scope.
hub_test/constrs/hub_test.xdc diff | blob | history
hub_test/src/hub_test.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware