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(parent: d70d53c) | patch
Use mpartcre to find designs without timing errors
authorAndreas Neiser <neiser@kph.uni-mainz.de>
Mon, 9 Feb 2015 12:52:34 +0000 (13:52 +0100)
committerAndreas Neiser <neiser@kph.uni-mainz.de>
Sat, 13 Jun 2015 15:36:55 +0000 (17:36 +0200)
commit4fb56244d39df2cc9baf41a8e7adf74707d298b4
treeebbacd7eefc05f773a3c6456ab42be3d1d804169tree | snapshot
parentd70d53ce1724ead86042556c4b0c0f981bd15f87commit | diff
Use mpartcre to find designs without timing errors
ADC/compile_periph_gsi.pl diff | blob | history
ADC/nodelist.txt [new file with mode: 0644] blob
ADC/trb3_periph_adc.p2t [new file with mode: 0644] blob
ADC/trb3_periph_adc.p3t [new file with mode: 0644] blob
TRB3 VHDL