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(parent: 0ee43e7) | patch
changed constraints for the spi logic for easier placement
authorCahit <c.ugur@gsi.de>
Sat, 15 Mar 2014 06:52:29 +0000 (07:52 +0100)
committerCahit <c.ugur@gsi.de>
Sat, 15 Mar 2014 06:52:29 +0000 (07:52 +0100)
commit53dfc881e620f94b7f5f26a3c3fcb5c1582049ed
tree9d1444254303ad358850d8b29a79a0b8bb8ffdd2tree | snapshot
parent0ee43e75a6d88d05485f1b1aefe16eee5a345e5bcommit | diff
changed constraints for the spi logic for easier placement
tdc_releases/tdc_v1.6/trbnet_constraints.lpf diff | blob | history
TRB3 VHDL