jspc29.x-matter.uni-frankfurt.de Git

]> jspc29.x-matter.uni-frankfurt.de Git - tdc.git/commit

author	Cahit <c.ugur@gsi.de>
	Fri, 11 Sep 2015 09:23:52 +0000 (11:23 +0200)
committer	Cahit <c.ugur@gsi.de>
	Fri, 11 Sep 2015 09:23:52 +0000 (11:23 +0200)
commit	54e7f902f553e8ca013eda349b3d3539e412f84b
tree	b7f45cddc5110af1ce6b8b46175f0a28cde04db1	tree \| snapshot
parent	2cb54e200e9530ef1bc9dd08b3a98f5735b8c600	commit \| diff

added new FIFO cores

49 files changed:

base/cores/ecp3/FIFO/._Real_._Math_.vhd	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.edn	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.ipx	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.jhd	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.lpc	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.naf	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.sort	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.srp	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.sym	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.vhd	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg_generate.log	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg_tmpl.vhd	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.edn		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.ipx		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.jhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.lpc		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.naf	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.srp		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.sym	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg_generate.log		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x128_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.edn		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.ipx		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.jhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.lpc		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.naf	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.srp		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.sym	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg_generate.log		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x32_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.edn		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.ipx		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.jhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.lpc		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.naf	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.srp		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.sym	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg_generate.log		diff \| blob \| history
base/cores/ecp3/FIFO/FIFO_36x64_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/generate_core.tcl		diff \| blob \| history
base/cores/ecp3/FIFO/generate_ngd.tcl		diff \| blob \| history
base/cores/ecp3/FIFO/msg_file.log		diff \| blob \| history
base/cores/ecp3/FIFO/tb_FIFO_36x128_DynThr_OutReg_tmpl.vhd	[new file with mode: 0644]	blob
base/cores/ecp3/FIFO/tb_FIFO_36x128_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/tb_FIFO_36x32_OutReg_tmpl.vhd		diff \| blob \| history
base/cores/ecp3/FIFO/tb_FIFO_36x64_OutReg_tmpl.vhd		diff \| blob \| history

The FPGA-TDC files

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