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(parent: e696912) | patch
Add new calibration PLL for DiRich 3
authorJan Michel <j.michel@gsi.de>
Tue, 3 Apr 2018 11:52:13 +0000 (13:52 +0200)
committerJan Michel <j.michel@gsi.de>
Tue, 3 Apr 2018 11:52:13 +0000 (13:52 +0200)
commit564d73a1336b95f8b7bd46295d179444aca8dc99
tree965f9d29184bd01e9190925d4b7beafb9703047etree | snapshot
parente69691286f21f8e7ad1be6a9f9a41f5dbf934303commit | diff
Add new calibration PLL for DiRich 3
base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.lpc [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.sbx [new file with mode: 0644] blob
base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd [new file with mode: 0644] blob
The FPGA-TDC files