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(parent: 8aebe9e) | patch
adding debug UART to CTS project. I/O on TEST_LINE(31..30) = J6 pin 4+5
authorJan Michel <j.michel@gsi.de>
Wed, 9 Dec 2015 17:45:31 +0000 (18:45 +0100)
committerJan Michel <j.michel@gsi.de>
Wed, 9 Dec 2015 17:45:31 +0000 (18:45 +0100)
commit57524b8a33c583321f1dfd4829ff788ccc22ca6e
treee523e4e1a467eacbea912c9372c615eebc8277bbtree | snapshot
parent8aebe9ef430faff07711c196011cbb70ec29e251commit | diff
adding debug UART to CTS project. I/O on TEST_LINE(31..30) = J6 pin 4+5
base/trb3_central_cts.lpf diff | blob | history
cts/config_cbmtof.vhd diff | blob | history
cts/trb3_central.prj diff | blob | history
cts/trb3_central.vhd diff | blob | history
TRB3 VHDL