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(parent: b353b41) | patch
new FIFO module
authorCahit <c.ugur@gsi.de>
Wed, 7 Oct 2015 14:07:56 +0000 (16:07 +0200)
committerCahit <c.ugur@gsi.de>
Wed, 7 Oct 2015 14:07:56 +0000 (16:07 +0200)
commit5d010dd7c6f292fe9ba4fdab307a850d761e45ca
treef40d9661f929cefbed9ed220994be01794201474tree | snapshot
parentb353b41e364af0817f887c468dcca0ac56a8901fcommit | diff
new FIFO module
15 files changed:
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.edn [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.ipx [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.jhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.lpc [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.naf [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.sort [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.srp [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.sym [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg_generate.log [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg_tmpl.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/generate_core.tcl diff | blob | history
base/cores/ecp3/FIFO/generate_ngd.tcl diff | blob | history
base/cores/ecp3/FIFO/msg_file.log diff | blob | history
base/cores/ecp3/FIFO/tb_FIFO_DC_36x64_DynThr_OutReg_tmpl.vhd [new file with mode: 0644] blob
The FPGA-TDC files