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(parent: 1a9da8e) | patch
Adapt TrbNet-DCA bridge for synthesis
authorThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Tue, 23 Mar 2021 15:15:46 +0000 (16:15 +0100)
committerThomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
Tue, 23 Mar 2021 15:21:00 +0000 (16:21 +0100)
commit6a3d1a49ab9a75853cd45e36a3b424af3ec0bdd6
treeb9a5a6653739d05349b5d1e5ef319e67c61433cbtree | snapshot
parent1a9da8e6c7afa24b5a46ab69218428e0fe19c6d4commit | diff
Adapt TrbNet-DCA bridge for synthesis

This includes the addition of XCKU FIFO cores and some changes to the
HDL codes. This likely breaks the current simulation testbench, which
will have to be fixed in a future commit.
src/DCA_cores/xcku/.gitignore [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_2kx34x17_wcnt_xcku/fifo_2kx34x17_wcnt_xcku.xci [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_4kx16x32_wcnt_xcku/fifo_4kx16x32_wcnt_xcku.xci [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd [new file with mode: 0644] blob
src/DCA_cores/xcku/fifo_64kx16x32_wcnt_xcku/fifo_64kx16x32_wcnt_xcku.xci [new file with mode: 0644] blob
src/agwb_handler_dca_sim.vhd diff | blob | history
src/cri_trbnet_dca_bridge.vhd diff | blob | history
src/cri_trbnet_dca_bridge_handler.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware