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(parent: 42cf36d) | patch
correct clock names for the multicycle constraint
authorCahit <c.ugur@gsi.de>
Tue, 22 Apr 2014 13:28:38 +0000 (15:28 +0200)
committerCahit <c.ugur@gsi.de>
Tue, 22 Apr 2014 13:28:38 +0000 (15:28 +0200)
commit6c836f98d7c01bd057839b8e6ba578c86fcee7d9
tree1364b8079a8fb4c23ca9631933dd3ee7d0dd1259tree | snapshot
parent42cf36d7252edcbaef0caafd3b7b747c0e250ce7commit | diff
correct clock names for the multicycle constraint
base/trb3_periph_32PinAddOn.lpf diff | blob | history
TRB3 VHDL