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(parent: ad76acf) | patch
added FIFOs for ecp3
authorCahit <c.ugur@gsi.de>
Fri, 17 Apr 2015 08:39:14 +0000 (10:39 +0200)
committerCahit <c.ugur@gsi.de>
Fri, 17 Apr 2015 08:39:14 +0000 (10:39 +0200)
commit717c920a479fbcf00c5559332d76b353534e1377
tree1ddc2c5623c44ace7c9f448404e6b8ab154501bdtree | snapshot
parentad76acf60ccaf2de54d9a5550b59428f7de63cf3commit | diff
added FIFOs for ecp3
28 files changed:
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.edn [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.ipx [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.jhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.lpc [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.sort [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.srp [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg_generate.log [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_36x128_OutReg_tmpl.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.edn [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.ipx [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.jhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.lpc [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.sort [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.srp [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_generate.log [new file with mode: 0644] blob
base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/generate_core.tcl [new file with mode: 0644] blob
base/cores/ecp3/FIFO/generate_ngd.tcl [new file with mode: 0644] blob
base/cores/ecp3/FIFO/msg_file.log [new file with mode: 0644] blob
base/cores/ecp3/FIFO/tb_FIFO_36x128_OutReg_tmpl.vhd [new file with mode: 0644] blob
base/cores/ecp3/FIFO/tb_FIFO_DC_36x128_DynThr_OutReg_tmpl.vhd [new file with mode: 0644] blob
base/cores/ecp3/TDC/ROM_encoder_3.vhd [new file with mode: 0644] blob
releases/tdc_v2.1.2/ROM_encoder_ecp3.vhd [new symlink] blob
releases/tdc_v2.1.2/ROM_encoder_ecp5.vhd [moved from releases/tdc_v2.1.2/ROM_encoder_3.vhd with 100% similarity] blob | history
releases/tdc_v2.1.2/tdc_constraints_64.lpf diff | blob | history
releases/tdc_v2.1.2/unimportant_lines_constraints.lpf diff | blob | history
The FPGA-TDC files