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(parent: 41d7e25) | patch
fix for data_ready signal and resulting 50% data acceptance. additional signal init...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Fri, 12 Feb 2021 13:41:13 +0000 (14:41 +0100)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Fri, 12 Feb 2021 13:41:13 +0000 (14:41 +0100)
commit7930f38b2dc36dc44c7d48564a19938dfb4c88a7
treef6f06b8f5b0b7d2e18aad28e09a61753ebcc071btree | snapshot
parent41d7e25b301d468ae14d6b3613158e68d266a326commit | diff
fix for data_ready signal and resulting 50% data acceptance. additional signal init values and reset for state machine
src/DLM_CTS_generator.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware