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(parent: 4fc86d4) | patch
fix of a bug in reset of trbnet from trbnet bridge. The sync from AGWB is mostly...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Mon, 26 Apr 2021 06:23:02 +0000 (08:23 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Mon, 26 Apr 2021 06:23:02 +0000 (08:23 +0200)
commit79eb8f822d56ce1bfd0171c7f27fba7436dcbd78
tree65bfeb024233be0ca275044c18dc57bfe0cb1f31tree | snapshot
parent4fc86d48ffdf8bda8d94c8868273afdf32f7c5d0commit | diff
fix of a bug in reset of trbnet from trbnet bridge. The sync from AGWB is mostly getting high for a few ns after reset. A timeout of a few ns resolves this issue for now.
src/cri_trbnet_dca_bridge.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware