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(parent: de1b4f5) | patch
spi interface with 2 clocks, IF
authorIngo Froehlich <ingo@nomail.fake>
Tue, 6 Mar 2018 21:20:50 +0000 (22:20 +0100)
committerIngo Froehlich <ingo@nomail.fake>
Tue, 6 Mar 2018 21:20:50 +0000 (22:20 +0100)
commit7bfb84eb2359382310b3fd94b952a02534565735
tree4f6f102b423f2a9236cbf2d4c1fbf235efaf088btree | snapshot
parentde1b4f5c6cd6d0345222382dce22e44d2bbaadcbcommit | diff
spi interface with 2 clocks, IF
interface/spi_slave_async.vhd [new file with mode: 0644] blob
VHDL modules used by various projects