]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commit
trigger logic slow control address correction
authorCahit <c.ugur@gsi.de>
Mon, 10 Mar 2014 09:44:42 +0000 (10:44 +0100)
committerCahit <c.ugur@gsi.de>
Mon, 10 Mar 2014 09:44:42 +0000 (10:44 +0100)
commit7d352cc6b80bcf6d841f3003403daa76374695fd
treedaf6660b2db732dee78b2fc23c5ef559c6150e0c
parent5a4910f63e2dfe37ad587f00ac82d87cc946af23
trigger logic slow control address correction
32PinAddOn/trb3_periph_32PinAddOn.vhd
wasa/trb3_periph_padiwa.vhd