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(parent: b6a1790) | patch
add PLL for 200 MHz calibration oscillator
authorJan Michel <j.michel@gsi.de>
Mon, 19 Nov 2018 10:25:06 +0000 (11:25 +0100)
committerJan Michel <j.michel@gsi.de>
Mon, 19 Nov 2018 10:25:06 +0000 (11:25 +0100)
commit823bf741275fe21f73d39159e9dae5c549a630d7
tree7ea54664dda5e9eee773838daa819b03f4219827tree | snapshot
parentb6a1790e3b81baf10893f5859cc29ae1a96f908ecommit | diff
add PLL for 200 MHz calibration oscillator
base/cores/ecp3/PLL/pll_in200_out33.ipx [new file with mode: 0644] blob
base/cores/ecp3/PLL/pll_in200_out33.lpc [new file with mode: 0644] blob
base/cores/ecp3/PLL/pll_in200_out33.vhd [new file with mode: 0644] blob
The FPGA-TDC files