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(parent: 9490f9d) | patch
set Trbnet Bridge Port to stream port. Reorder data in xilinx fifo wrapper to match...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 6 Apr 2021 08:43:30 +0000 (10:43 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 6 Apr 2021 08:43:30 +0000 (10:43 +0200)
commit882cf050f1926b99f882dc0017944f5e8fd8c809
tree414588332d88c6f63c40750d612ac7cd65758c3atree | snapshot
parent9490f9d8c6c3c46baa92f3ed3b74f9eef368179ccommit | diff
set Trbnet Bridge Port to stream port. Reorder data in xilinx fifo wrapper to match lattice definition and allow for correct data transmission
src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd diff | blob | history
src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd diff | blob | history
src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd diff | blob | history
src/hub/trb_net16_cri_hub.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware