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(parent: 7930f38) | patch
DLM_CTS_generator: deactivation of constant CLM_ready signal. Now controlled active...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Fri, 12 Feb 2021 16:39:07 +0000 (17:39 +0100)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Fri, 12 Feb 2021 16:39:07 +0000 (17:39 +0100)
commit8aa91579cd8062e5ce59654d0c89392c31770a77
treee8160435a8d6ab93abd3a646c750521c50b298abtree | snapshot
parent7930f38b2dc36dc44c7d48564a19938dfb4c88a7commit | diff
DLM_CTS_generator: deactivation of constant CLM_ready signal. Now controlled active by DLM signal.
src/DLM_CTS_generator.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware