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(parent: 2093de1) | patch
Added ADC design files
authorJan Michel <j.michel@gsi.de>
Mon, 3 Feb 2014 17:43:17 +0000 (18:43 +0100)
committerJan Michel <j.michel@gsi.de>
Mon, 3 Feb 2014 17:45:01 +0000 (18:45 +0100)
commit9199a2c82fea081387714184f38740bc39cfa289
tree293482d9a5aaf01d240247354dc31a796767d82atree | snapshot
parent2093de16ffbcf8840807ed86a632177201c15a1ecommit | diff
Added ADC design files
15 files changed:
ADC/compile_periph_frankfurt.pl [new file with mode: 0755] blob
ADC/config.vhd [new file with mode: 0644] blob
ADC/trb3_periph_adc.prj [new file with mode: 0644] blob
ADC/trb3_periph_adc.vhd [new file with mode: 0644] blob
base/code/adc_ad9219.vhd [new file with mode: 0644] blob
base/cores/dqsinput_5x5.ipx [new file with mode: 0644] blob
base/cores/dqsinput_5x5.lpc [new file with mode: 0644] blob
base/cores/dqsinput_5x5.vhd [new file with mode: 0644] blob
base/cores/dqsinput_7x5.ipx [new file with mode: 0644] blob
base/cores/dqsinput_7x5.lpc [new file with mode: 0644] blob
base/cores/dqsinput_7x5.vhd [new file with mode: 0644] blob
base/cores/pll_adc10bit.ipx [new file with mode: 0644] blob
base/cores/pll_adc10bit.lpc [new file with mode: 0644] blob
base/cores/pll_adc10bit.vhd [new file with mode: 0644] blob
base/trb3_periph_adc.lpf [new file with mode: 0644] blob
TRB3 VHDL