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(parent: 6a3d1a4) | patch
fix of issue with dca bridge reset signal to get readout of registers working.
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 30 Mar 2021 14:04:04 +0000 (16:04 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 30 Mar 2021 14:04:04 +0000 (16:04 +0200)
commit9490f9d8c6c3c46baa92f3ed3b74f9eef368179c
treed9c818b66b96ce86d1d97beb22a6091648b2d8dftree | snapshot
parent6a3d1a49ab9a75853cd45e36a3b424af3ec0bdd6commit | diff
fix of issue with dca bridge reset signal to get readout of registers working.
src/cri_trbnet_dca_bridge_handler.vhd diff | blob | history
VHDL modules for TrbNet on CBM Xilinx hardware