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(parent: c8baded) | patch
Adding 200->65 MHz PLL
authorAndreas Neiser <neiser@kph.uni-mainz.de>
Tue, 10 Feb 2015 08:59:31 +0000 (09:59 +0100)
committerAndreas Neiser <neiser@kph.uni-mainz.de>
Sat, 13 Jun 2015 15:36:55 +0000 (17:36 +0200)
commit961c100ccba703a72a737dea5e35e0ff31ea6879
tree0523c63fa8bcfe874b35867aeb2f811b9f92fc91tree | snapshot
parentc8baded9b903635c1af936821ecc0bf44206cf28commit | diff
Adding 200->65 MHz PLL
base/cores/pll_in200_out65.ipx [new file with mode: 0644] blob
base/cores/pll_in200_out65.lpc [new file with mode: 0644] blob
base/cores/pll_in200_out65.vhd [new file with mode: 0644] blob
TRB3 VHDL