jspc29.x-matter.uni-frankfurt.de Git - cri.git/commit

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jspc29 / cri.git / commit

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(parent: 0e57dc6) | patch

author	Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
	Fri, 11 Sep 2020 14:18:25 +0000 (16:18 +0200)
committer	Thomas Gessler <Thomas.Gessler@exp2.physik.uni-giessen.de>
	Sat, 12 Sep 2020 07:58:34 +0000 (09:58 +0200)
commit	96a887dd27a824f6ba20321d2f6671961d606ee5
tree	0f497b7d2508ef63a1a641e6d2a861bfdd08e269	tree \| snapshot
parent	0e57dc604391db8f70d2f3b6f935269126f0513e	commit \| diff

Change to new MGT clocking scheme

13 files changed:

endpoint_test/constrs/endpoint_test.xdc		diff \| blob \| history
endpoint_test/endpoint_test.xpr		diff \| blob \| history
endpoint_test/src/endpoint_test.vhd		diff \| blob \| history
hub_test/bd/design_1/design_1.bd		diff \| blob \| history
hub_test/constrs/hub_test.xdc		diff \| blob \| history
hub_test/hub_test.xpr		diff \| blob \| history
hub_test/ip/clk_wiz_0/clk_wiz_0.xci		diff \| blob \| history
hub_test/ip/clk_wiz_0/clk_wiz_0.xml		diff \| blob \| history
hub_test/ip/clk_wiz_1/clk_wiz_1.xci	[new file with mode: 0644]	blob
hub_test/ip/clk_wiz_1/clk_wiz_1.xml	[new file with mode: 0644]	blob
hub_test/scripts/generate_software.tcl		diff \| blob \| history
hub_test/src/hub_test.vhd		diff \| blob \| history
hub_test/sw/init.c		diff \| blob \| history

VHDL modules for TrbNet on CBM Xilinx hardware