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(parent: 3e63ddc) | patch
tdc_v0.2 is added
authorhadaq <hadaq>
Wed, 9 May 2012 09:59:43 +0000 (09:59 +0000)
committerhadaq <hadaq>
Wed, 9 May 2012 09:59:43 +0000 (09:59 +0000)
commita3a19a49b1b1dde1cb40143015fa1c0db28c0230
tree9e35b0bc0d776ee10e44c148de1d0a9b55af71fctree | snapshot
parent3e63ddc8546ff5dee32e2eb5cee6551432042d7acommit | diff
tdc_v0.2 is added
19 files changed:
tdc_releases/tdc_v0.2/bit_file/trb3_periph.bit [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/documentations/TDC_data_format.pdf [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/documentations/trb3_ctrl_stat_regs.odt [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/lpf_file/trb3_periph_constraints.lpf [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/prj_file/trb3_periph.edf [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/prj_file/trb3_periph.prj [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/Adder_304.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/Channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/Encoder_304_Bit.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/FIFO_32x512_OutReg.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/ROM_FIFO.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/ROM_encoder_3.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/Reference_channel.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/TDC.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/bit_sync.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/corell.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/pll_100_in_5_out.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/trb3_periph.vhd [new file with mode: 0644] blob
tdc_releases/tdc_v0.2/source/up_counter.vhd [new file with mode: 0644] blob
TRB3 VHDL